From 0860c95d5c1bab676095e28f3a4afab5fd50d817 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Tue, 29 Apr 2014 14:29:28 -0700 Subject: [PATCH] i965: Actually emit PIPELINE_SELECT and 3DSTATE_VF_STATISTICS. For platforms using hardware contexts (currently Gen6+), we failed to emit PIPELINE_SELECT and 3DSTATE_VF_STATISTICS, instead emitting MI_NOOP for both. During one of the context initialization reordering patches, we accidentally moved brw_init_state before we set brw->CMD_PIPELINE_SELECT and brw->CMD_VF_STATISTICS. So, when brw_init_state uploaded initial GPU state (brw_init_state -> brw_upload_initial_gpu_state -> brw_upload_invariant_state), these would be 0 (MI_NOOP). Storing the commands in the context is not worthwhile. We have many generation checks in our state upload code, and for platforms with hardware contexts, this only gets called once per GL context anyway. The cost is negligable, and it's easy to botch context creation ordering. This may fix hangs on Gen6+ when using the media pipeline. Cc: "10.0 10.1" Signed-off-by: Kenneth Graunke Reviewed-by: Eric Anholt Reviewed-by: Ben Widawsky (cherry picked from commit ac30e1adb49ec6947f740b47d90f8403fe416314) Conflicts: src/mesa/drivers/dri/i965/brw_context.h --- src/mesa/drivers/dri/i965/brw_context.c | 8 -------- src/mesa/drivers/dri/i965/brw_context.h | 5 ----- src/mesa/drivers/dri/i965/brw_misc_state.c | 10 ++++++++-- 3 files changed, 8 insertions(+), 15 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 3d6ee6f3ed1..ef1ac4504da 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -707,14 +707,6 @@ brwCreateContext(gl_api api, brw_init_surface_formats(brw); - if (brw->is_g4x || brw->gen >= 5) { - brw->CMD_VF_STATISTICS = GM45_3DSTATE_VF_STATISTICS; - brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_GM45; - } else { - brw->CMD_VF_STATISTICS = GEN4_3DSTATE_VF_STATISTICS; - brw->CMD_PIPELINE_SELECT = CMD_PIPELINE_SELECT_965; - } - brw->max_vs_threads = devinfo->max_vs_threads; brw->max_gs_threads = devinfo->max_gs_threads; brw->max_wm_threads = devinfo->max_wm_threads; diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 53a72c25374..acb41d22c7b 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1190,11 +1190,6 @@ struct brw_context const struct gl_geometry_program *geometry_program; const struct gl_fragment_program *fragment_program; - /* hw-dependent 3DSTATE_VF_STATISTICS opcode */ - uint32_t CMD_VF_STATISTICS; - /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */ - uint32_t CMD_PIPELINE_SELECT; - /** * Platform specific constants containing the maximum number of threads * for each pipeline stage. diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 673a25d741c..6f47c61fd51 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -925,13 +925,17 @@ const struct brw_tracked_state brw_line_stipple = { void brw_upload_invariant_state(struct brw_context *brw) { + const bool is_965 = brw->gen == 4 && !brw->is_g4x; + /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */ if (brw->gen == 6) intel_emit_post_sync_nonzero_flush(brw); /* Select the 3D pipeline (as opposed to media) */ + const uint32_t _3DSTATE_PIPELINE_SELECT = + is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45; BEGIN_BATCH(1); - OUT_BATCH(brw->CMD_PIPELINE_SELECT << 16 | 0); + OUT_BATCH(_3DSTATE_PIPELINE_SELECT << 16 | 0); ADVANCE_BATCH(); if (brw->gen < 6) { @@ -955,8 +959,10 @@ brw_upload_invariant_state(struct brw_context *brw) ADVANCE_BATCH(); } + const uint32_t _3DSTATE_VF_STATISTICS = + is_965 ? GEN4_3DSTATE_VF_STATISTICS : GM45_3DSTATE_VF_STATISTICS; BEGIN_BATCH(1); - OUT_BATCH(brw->CMD_VF_STATISTICS << 16 | + OUT_BATCH(_3DSTATE_VF_STATISTICS << 16 | (unlikely(INTEL_DEBUG & DEBUG_STATS) ? 1 : 0)); ADVANCE_BATCH(); }