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r600: fix cayman main non-deterministic behavior problem

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Cayman has a non-deterministic behavior issue which is
visible with the test below (arb_shader_image_size).
The tests fail randomly at the "fragment" test category.
Anyway, if the "compute" category is removed, the same
tests are working flawlessly.

The "compute" part of the driver was interfering with the
graphic pipeline. The culprit is the packet PKT3_DEALLOC_STATE
which puts the gpu in an incorrect state to perform some
graphic operations.

This change fixes this problem by issuing a PKT3_CLEAR_STATE
packet just after the PKT3_SURFACE_SYNC packet. As explained
by d51dbe048a PKT3_DEALLOC_STATE is mandatory on cayman to
avoid a gpu hang at the PKT3_SURFACE_SYNC stage.

This correction makes tests like
"spec@glsl-4.30@execution@built-in-functions@cs-.*" to pass
in an utterly deterministic way without random failures.
This change removes around 500 random failures for a
"piglit run all".

For instance, this issue is triggered on cayman with
"piglit/bin/arb_shader_image_size-builtin -auto -fbo".

Fixes: d51dbe048a ("r600g/compute: Emit DEALLOC_STATE on cayman after dispatching a compute shader.")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33973>
This commit is contained in:
Patrick Lerda 2025-03-07 12:47:30 +01:00 • committed by Marge Bot
parent 6f35d3768d
commit 085cfc98cc
4 changed files with 13 additions and 0 deletions
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1
src/gallium/drivers/r600/evergreen_compute.c
View file

@ -844,6 +844,7 @@ static void compute_emit_cs(struct r600_context *rctx,
*/
radeon_emit(cs, PKT3C(PKT3_DEALLOC_STATE, 0, 0));
radeon_emit(cs, 0);
rctx->cayman_dealloc_state = true;
}
if (rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_TGSI ||
rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_NIR)

10
src/gallium/drivers/r600/r600_hw_context.c
View file

@ -222,6 +222,16 @@ void r600_flush_emit(struct r600_context *rctx)
radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
radeon_emit(cs, 0); /* CP_COHER_BASE */
radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
/* PKT3_CLEAR_STATE below is required on cayman to set the gpu
* in a deterministic state after a compute shader. Otherwise,
* the graphic pipeline could fail in a non-deterministic way.
* See https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33973 */
if (unlikely(rctx->cayman_dealloc_state)) {
radeon_emit(cs, PKT3C(PKT3_CLEAR_STATE, 0, 0));
radeon_emit(cs, 0);
rctx->cayman_dealloc_state = false;
}
}
if (rctx->b.flags & R600_CONTEXT_START_PIPELINE_STATS) {

1
src/gallium/drivers/r600/r600_pipe.h
View file

@ -609,6 +609,7 @@ struct r600_context {
bool cmd_buf_is_compute;
struct pipe_resource *append_fence;
uint32_t append_fence_id;
bool cayman_dealloc_state;
};
static inline void r600_emit_command_buffer(struct radeon_cmdbuf *cs,

1
src/gallium/drivers/r600/r600d.h
View file

@ -36,6 +36,7 @@
#define PKT3_NOP 0x10
#define EG_PKT3_SET_BASE 0x11 /* >= evergreen */
#define EG_DRAW_INDEX_INDIRECT_PATCH_TABLE_BASE 1 /* DX11 Draw_Index_Indirect Patch Table Base */
#define PKT3_CLEAR_STATE 0x12
#define EG_PKT3_INDEX_BUFFER_SIZE 0x13
#define PKT3_INDIRECT_BUFFER_END 0x17
#define PKT3_SET_PREDICATION 0x20