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radv/winsys: simplify the user fence logic for submission
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8859>
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05c383f948
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1 changed files with 10 additions and 31 deletions
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@ -139,11 +139,6 @@ struct radv_amdgpu_cs_request {
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* The returned sequence number for the command submission
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*/
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uint64_t seq_no;
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/**
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* The fence information
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*/
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struct amdgpu_cs_fence_info fence_info;
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};
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@ -850,16 +845,6 @@ radv_amdgpu_get_bo_list(struct radv_amdgpu_winsys *ws,
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return VK_SUCCESS;
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}
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static struct amdgpu_cs_fence_info radv_set_cs_fence(struct radv_amdgpu_ctx *ctx, int ip_type, int ring)
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{
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struct amdgpu_cs_fence_info ret = {0};
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if (ctx->fence_map) {
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ret.handle = radv_amdgpu_winsys_bo(ctx->fence_bo)->bo;
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ret.offset = (ip_type * MAX_RINGS_PER_TYPE + ring) * sizeof(uint64_t);
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}
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return ret;
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}
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static void radv_assign_last_submit(struct radv_amdgpu_ctx *ctx,
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struct radv_amdgpu_cs_request *request)
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{
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@ -936,7 +921,6 @@ radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
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request.ibs = ibs;
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request.handles = handles;
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request.num_handles = num_handles;
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request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
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/* Submit the CS. */
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result = radv_amdgpu_cs_submit(ctx, &request, sem_info);
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@ -1024,7 +1008,6 @@ radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
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request.num_handles = num_handles;
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request.number_of_ibs = number_of_ibs;
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request.ibs = ibs;
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request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
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/* Submit the CS. */
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result = radv_amdgpu_cs_submit(ctx, &request, sem_info);
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@ -1224,7 +1207,6 @@ radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
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request.num_handles = num_handles;
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request.number_of_ibs = number_of_ibs;
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request.ibs = ibs;
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request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
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sem_info->cs_emit_signal = (i == cs_count - cnt) ? emit_signal_sem : false;
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result = radv_amdgpu_cs_submit(ctx, &request, sem_info);
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@ -1618,7 +1600,6 @@ radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
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int r;
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int num_chunks;
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int size;
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bool user_fence;
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struct drm_amdgpu_cs_chunk *chunks;
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struct drm_amdgpu_cs_chunk_data *chunk_data;
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struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL;
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@ -1631,14 +1612,13 @@ radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
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uint32_t bo_list = 0;
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VkResult result = VK_SUCCESS;
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user_fence = (request->fence_info.handle != NULL);
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size = request->number_of_ibs + (user_fence ? 2 : 1) + (!use_bo_list_create ? 1 : 0) + 3;
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size = request->number_of_ibs + 2 /* user fence */ + (!use_bo_list_create ? 1 : 0) + 3;
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chunks = malloc(sizeof(chunks[0]) * size);
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if (!chunks)
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return VK_ERROR_OUT_OF_HOST_MEMORY;
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size = request->number_of_ibs + (user_fence ? 1 : 0);
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size = request->number_of_ibs + 1 /* user fence */;
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chunk_data = malloc(sizeof(chunk_data[0]) * size);
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if (!chunk_data) {
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@ -1664,16 +1644,15 @@ radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx,
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chunk_data[i].ib_data.flags = ib->flags;
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}
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if (user_fence) {
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i = num_chunks++;
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i = num_chunks++;
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chunks[i].chunk_id = AMDGPU_CHUNK_ID_FENCE;
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chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4;
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chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
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chunks[i].chunk_id = AMDGPU_CHUNK_ID_FENCE;
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chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4;
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chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
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amdgpu_cs_chunk_fence_info_to_data(&request->fence_info,
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&chunk_data[i]);
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}
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struct amdgpu_cs_fence_info fence_info;
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fence_info.handle = radv_amdgpu_winsys_bo(ctx->fence_bo)->bo;
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fence_info.offset = (request->ip_type * MAX_RINGS_PER_TYPE + request->ring) * sizeof(uint64_t);
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amdgpu_cs_chunk_fence_info_to_data(&fence_info, &chunk_data[i]);
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if ((sem_info->wait.syncobj_count || sem_info->wait.timeline_syncobj_count) && sem_info->cs_emit_wait) {
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r = radv_amdgpu_cs_prepare_syncobjs(ctx->ws, &sem_info->wait, &in_syncobjs);
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