From 08429da731282f0a2987f784116a9ab1a55463d2 Mon Sep 17 00:00:00 2001 From: Sagar Ghuge Date: Thu, 12 Aug 2021 11:37:26 -0700 Subject: [PATCH] intel/genxml: Add L1 Cache Control bit field Add L1 cache control bit field to RENDER_SURFACE_STATE and STATE_BASE_ADDRESS instruction. v1: (Jason) - Add prefix to bit field - Don't miss out STATE_BASE_ADDRESS instruction Signed-off-by: Sagar Ghuge Reviewed-by: Jason Ekstrand Reviewed-by: Kenneth Graunke Part-of: --- src/intel/genxml/gen125.xml | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml index b24dd4ec846..78ed40fd90f 100644 --- a/src/intel/genxml/gen125.xml +++ b/src/intel/genxml/gen125.xml @@ -817,6 +817,13 @@ + + + + + + + @@ -6992,6 +6999,13 @@ + + + + + + +