From 081efcd68decea7e3f47b41d2e611aa4cea857d7 Mon Sep 17 00:00:00 2001
From: Christian Gmeiner <cgmeiner@igalia.com>
Date: Tue, 3 Mar 2026 19:52:39 +0100
Subject: [PATCH] etnaviv: isa: Split texkill into concrete bitset variants

Replace the #instruction-alu-no-dst-maybe-src0-src1 intermediate, which
used override expressions and variable SRC USE fields, with two concrete
intermediates following the branch/branch_unary/branch_binary pattern:

- #instruction-alu-no-dst-no-src: no sources, COND bits forced to zero
- #instruction-alu-no-dst-cond-src0-src1: SRC0+SRC1 with fixed USE=1
  patterns and a COND field

The texkill instruction is split into texkill (unconditional, no sources)
and texkill_cond (conditional, with sources). This eliminates the "maybe"
anti-pattern and enables full assembler round-trip for conditional texkill.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40205>
---
 src/etnaviv/isa/etnaviv.xml      | 76 +++++++++++++++++++++-----------
 src/etnaviv/isa/tests/disasm.cpp |  2 +-
 2 files changed, 51 insertions(+), 27 deletions(-)

diff --git a/src/etnaviv/isa/etnaviv.xml b/src/etnaviv/isa/etnaviv.xml
index 6f4fa0a79aa..ff74ff1bdd1 100644
--- a/src/etnaviv/isa/etnaviv.xml
+++ b/src/etnaviv/isa/etnaviv.xml
@@ -374,10 +374,6 @@ SPDX-License-Identifier: MIT
 	<pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP -->
 </bitset>
 
-<expr name="#instruction-has-src0-src1">
-     ({SRC0_USE} != 0) &amp;&amp; ({SRC1_USE} != 0)
-</expr>
-
 <expr name="#instruction-has-src2">
      ({SRC2_USE} != 0)
 </expr>
@@ -386,33 +382,52 @@ SPDX-License-Identifier: MIT
      ({SRC0_USE} != 0) &amp;&amp; ({SRC1_USE} != 0)  &amp;&amp; ({SRC2_USE} != 0)
 </expr>
 
-<bitset name="#instruction-alu-no-dst-maybe-src0-src1" extends="#instruction-alu">
-	<doc>Needed for texkill</doc>
+<bitset name="#instruction-alu-no-dst-no-src" extends="#instruction-alu">
+	<pattern low="6" high="10">00000</pattern>
+
+	<display>
+		{INSTR_ALU} {DST:align=18}, void, void, void
+	</display>
+
+	<!-- SRC0 -->
+	<pattern pos="43">0</pattern> <!-- SRC0_USE -->
+	<pattern low="44" high="52">000000000</pattern> <!-- SRC0_REG -->
+	<pattern low="54" high="61">00000000</pattern> <!-- SRC0_SWIZ -->
+	<pattern pos="62">0</pattern> <!-- SRC0_NEG -->
+	<pattern pos="63">0</pattern> <!-- SRC0_ABS -->
+	<pattern low="64" high="66">000</pattern> <!-- SRC0_AMODE -->
+	<pattern low="67" high="69">000</pattern> <!-- SRC0_RGROUP -->
+
+	<!-- SRC1 -->
+	<pattern pos="70">0</pattern> <!-- SRC1_USE -->
+	<pattern low="71" high="79">000000000</pattern> <!-- SRC1_REG -->
+	<pattern low="81" high="88">00000000</pattern> <!-- SRC1_SWIZ -->
+	<pattern pos="89">0</pattern> <!-- SRC1_NEG -->
+	<pattern pos="90">0</pattern> <!-- SRC1_ABS -->
+	<pattern low="91" high="93">000</pattern> <!-- SRC1_AMODE -->
+	<pattern low="96" high="98">000</pattern> <!-- SRC1_RGROUP -->
+
+	<!-- SRC2 -->
+	<pattern pos="99">0</pattern> <!-- SRC2_USE -->
+	<pattern low="100" high="108">000000000</pattern> <!-- SRC2_REG -->
+	<pattern low="110" high="117">00000000</pattern> <!-- SRC2_SWIZ -->
+	<pattern pos="118">0</pattern> <!-- SRC2_NEG -->
+	<pattern pos="119">0</pattern> <!-- SRC2_ABS -->
+	<pattern low="121" high="123">000</pattern> <!-- SRC2_AMODE -->
+	<pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP -->
+</bitset>
+
+<bitset name="#instruction-alu-no-dst-cond-src0-src1" extends="#instruction-alu">
+	<meta type="alu_cond" has_dest="false" valid_srcs="0|1"/>
 
 	<field name="COND" low="6" high="10" type="#cond"/>
 
-	<encode type="struct etna_inst *" case-prefix="ISA_OPC_">
-		<map name="COND">src->cond</map>
-	</encode>
-
 	<display>
-		{NAME}{COND}{TYPE}{PMODE}{THREAD}{RMODE} {DST:align=18}{DST_FULL}, void, void, void
+		{INSTR_ALU_COND} {DST:align=18}, {SRC0}, {SRC1}, void
 	</display>
 
-	<override expr="#instruction-has-src0-src1">
-		<display>
-			{NAME}{COND}{TYPE}{PMODE}{THREAD}{RMODE} {DST:align=18}, {SRC0}, {SRC1}, void
-		</display>
-	</override>
-
-	<override expr="#instruction-has-src0">
-		<display>
-			{NAME}{COND}{TYPE}{PMODE}{THREAD}{RMODE} {DST:align=18}, {SRC0}, void, void
-		</display>
-	</override>
-
 	<!-- SRC0 -->
-	<field name="SRC0_USE" pos="43" type="bool"/>
+	<pattern pos="43">1</pattern> <!-- SRC0_USE -->
 	<field name="SRC0_REG" low="44" high="52" type="uint"/>
 	<field name="SRC0" low="54" high="63" type="#instruction-src">
 		<param name="SRC0_REG" as="SRC_REG"/>
@@ -423,7 +438,7 @@ SPDX-License-Identifier: MIT
 	<field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/>
 
 	<!-- SRC1 -->
-	<field name="SRC1_USE" pos="70" type="bool"/>
+	<pattern pos="70">1</pattern> <!-- SRC1_USE -->
 	<field name="SRC1_REG" low="71" high="79" type="uint"/>
 	<field name="SRC1" low="81" high="90" type="#instruction-src">
 		<param name="SRC1_REG" as="SRC_REG"/>
@@ -441,6 +456,10 @@ SPDX-License-Identifier: MIT
 	<pattern pos="119">0</pattern> <!-- SRC2_ABS -->
 	<pattern low="121" high="123">000</pattern> <!-- SRC2_AMODE -->
 	<pattern low="124" high="126">000</pattern> <!-- SRC2_RGROUP -->
+
+	<encode type="struct etna_inst *" case-prefix="ISA_OPC_">
+		<map name="COND">src->cond</map>
+	</encode>
 </bitset>
 
 <bitset name="#instruction-alu-src0" extends="#instruction-alu">
@@ -1376,7 +1395,12 @@ SPDX-License-Identifier: MIT
 	<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
 </bitset>
 
-<bitset name="texkill" extends="#instruction-alu-no-dst-maybe-src0-src1">
+<bitset name="texkill" extends="#instruction-alu-no-dst-no-src">
+	<pattern low="0" high="5">010111</pattern> <!-- OPC -->
+	<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
+</bitset>
+
+<bitset name="texkill_cond" extends="#instruction-alu-no-dst-cond-src0-src1" displayname="texkill">
 	<pattern low="0" high="5">010111</pattern> <!-- OPC -->
 	<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
 </bitset>
diff --git a/src/etnaviv/isa/tests/disasm.cpp b/src/etnaviv/isa/tests/disasm.cpp
index 9e8051348c7..d32e4fc20e2 100644
--- a/src/etnaviv/isa/tests/disasm.cpp
+++ b/src/etnaviv/isa/tests/disasm.cpp
@@ -141,7 +141,7 @@ INSTANTIATE_TEST_SUITE_P(Opcodes, DisasmTest,
       disasm_state{ {0x00000015, 0x00000000, 0x00000000, 0x00000000}, "ret               void, void, void, void\n" },
       disasm_state{ {0x00000016, 0x00000000, 0x00000000, 0x00001080}, "branch            void, void, void, 33\n"},
       disasm_state{ {0x00000017, 0x00000000, 0x00000000, 0x00000000}, "texkill.pack      void, void, void, void\n" },
-      disasm_state{ {0x00000057, 0x00002800, 0x00000040, 0x00000002}, "texkill.gt.pack   void, t2.xxxx, u0.xxxx, void\n", FLAG_FAILING_PARSE | FLAG_FAILING_ASM },
+      disasm_state{ {0x00000057, 0x00002800, 0x00000040, 0x00000002}, "texkill.gt.pack   void, t2.xxxx, u0.xxxx, void\n" },
       disasm_state{ {0x07811018, 0x15001f20, 0x00000000, 0x00000000}, "texld             t1, tex0.xyzw, t1.xyyy, void, void\n" },
       disasm_state{ {0x07811019, 0x39002f20, 0x00000000, 0x00000000}, "texldb            t1, tex0.xyzw, t2.xyzw, void, void\n", FLAG_FAILING_PARSE | FLAG_FAILING_ASM },
       disasm_state{ {0x0781101a, 0x15001f20, 0x00a80140, 0x003f8018}, "texldd            t1, tex0.xyzw, t1.xyyy, t2.xyyy, t1.zwww\n" },