From 0813c1a6fa5aae6e97e6f54822105ce345592c88 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tapani=20P=C3=A4lli?= <tapani.palli@intel.com>
Date: Mon, 23 Jan 2023 10:57:20 +0200
Subject: [PATCH] intel/genxml: set unused 3DSTATE_PS_EXTRA field as mbz
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Wa_14015360517 mentions situations where HW produces invalid
occlusion query results when "Pixel Shader Does not write to RT"
bit is set.

"When Pixel Shader Kills Pixel is set, SW must perform a dummy render
 target write from the shader and not set this bit, so that Occlusion
 Query is correct."

Another situation is when writing to UAV or to NULL render target.
Patch sets field as 'must be zero' to discourage possible use of it.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20849>
---
 src/intel/genxml/gen11.xml  | 2 +-
 src/intel/genxml/gen12.xml  | 4 ++--
 src/intel/genxml/gen125.xml | 2 +-
 src/intel/genxml/gen8.xml   | 4 ++--
 src/intel/genxml/gen9.xml   | 4 ++--
 5 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 3450f821c6f..6472fd402dd 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -2062,7 +2062,7 @@
     </field>
     <field name="Pixel Shader Kills Pixel" start="60" end="60" type="bool" />
     <field name="oMask Present to Render Target" start="61" end="61" type="bool" />
-    <field name="Pixel Shader Does not write to RT" start="62" end="62" type="bool" />
+    <field name="Pixel Shader Does not write to RT" start="62" end="62" type="mbz" />
     <field name="Pixel Shader Valid" start="63" end="63" type="bool" />
   </instruction>
   <instruction name="3DSTATE_PUSH_CONSTANT_ALLOC_DS" bias="2" length="2" engine="render">
diff --git a/src/intel/genxml/gen12.xml b/src/intel/genxml/gen12.xml
index 5f0858e1dfd..76c9e5be7bf 100644
--- a/src/intel/genxml/gen12.xml
+++ b/src/intel/genxml/gen12.xml
@@ -2137,7 +2137,7 @@
     </field>
     <field name="Pixel Shader Kills Pixel" start="60" end="60" type="bool" />
     <field name="oMask Present to Render Target" start="61" end="61" type="bool" />
-    <field name="Pixel Shader Does not write to RT" start="62" end="62" type="bool" />
+    <field name="Pixel Shader Does not write to RT" start="62" end="62" type="mbz" />
     <field name="Pixel Shader Valid" start="63" end="63" type="bool" />
   </instruction>
   <instruction name="3DSTATE_PUSH_CONSTANT_ALLOC_DS" bias="2" length="2" engine="render">
@@ -7178,4 +7178,4 @@
   <register name="VS_INVOCATION_COUNT" length="2" num="0x2320">
     <field name="VS Invocation Count Report" start="0" end="63" type="uint" />
   </register>
-</genxml>
\ No newline at end of file
+</genxml>
diff --git a/src/intel/genxml/gen125.xml b/src/intel/genxml/gen125.xml
index d8ed8c90b08..fffb372fffa 100644
--- a/src/intel/genxml/gen125.xml
+++ b/src/intel/genxml/gen125.xml
@@ -2380,7 +2380,7 @@
     </field>
     <field name="Pixel Shader Kills Pixel" start="60" end="60" type="bool" />
     <field name="oMask Present to Render Target" start="61" end="61" type="bool" />
-    <field name="Pixel Shader Does not write to RT" start="62" end="62" type="bool" />
+    <field name="Pixel Shader Does not write to RT" start="62" end="62" type="mbz" />
     <field name="Pixel Shader Valid" start="63" end="63" type="bool" />
   </instruction>
   <instruction name="3DSTATE_PUSH_CONSTANT_ALLOC_DS" bias="2" length="2" engine="render">
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index 139729eea9f..6ba7dad52ca 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -1499,7 +1499,7 @@
     </field>
     <field name="Pixel Shader Kills Pixel" start="60" end="60" type="bool" />
     <field name="oMask Present to Render Target" start="61" end="61" type="bool" />
-    <field name="Pixel Shader Does not write to RT" start="62" end="62" type="bool" />
+    <field name="Pixel Shader Does not write to RT" start="62" end="62" type="mbz" />
     <field name="Pixel Shader Valid" start="63" end="63" type="bool" />
   </instruction>
   <instruction name="3DSTATE_PUSH_CONSTANT_ALLOC_DS" bias="2" length="2" engine="render">
@@ -4744,4 +4744,4 @@
   <register name="VS_INVOCATION_COUNT" length="2" num="0x2320">
     <field name="VS Invocation Count Report" start="0" end="63" type="uint" />
   </register>
-</genxml>
\ No newline at end of file
+</genxml>
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 0433af00853..e18fce31b99 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -1876,7 +1876,7 @@
     </field>
     <field name="Pixel Shader Kills Pixel" start="60" end="60" type="bool" />
     <field name="oMask Present to Render Target" start="61" end="61" type="bool" />
-    <field name="Pixel Shader Does not write to RT" start="62" end="62" type="bool" />
+    <field name="Pixel Shader Does not write to RT" start="62" end="62" type="mbz" />
     <field name="Pixel Shader Valid" start="63" end="63" type="bool" />
   </instruction>
   <instruction name="3DSTATE_PUSH_CONSTANT_ALLOC_DS" bias="2" length="2" engine="render">
@@ -6541,4 +6541,4 @@
   <register name="VS_INVOCATION_COUNT" length="2" num="0x2320">
     <field name="VS Invocation Count Report" start="0" end="63" type="uint" />
   </register>
-</genxml>
\ No newline at end of file
+</genxml>