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i965: Emit SNB FF unit state after the unit's push constants.

Browse source 
There's a BUN for the WM unit that says WM_STATE must immediately
follow PS_CONSTANTS, which this addresses.  Presumably other units are
roughly the same, too.
This commit is contained in:
Eric Anholt 2010-02-23 17:42:20 -08:00
parent c791f8a1e5
commit 078e7b62f6
3 changed files with 69 additions and 69 deletions
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22
src/mesa/drivers/dri/i965/gen6_gs_state.c
View file

@ -38,6 +38,17 @@ upload_gs_state(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
/* Disable all the constant buffers. */
BEGIN_BATCH(5);
OUT_BATCH(CMD_3D_CONSTANT_GS_STATE << 16 | (5 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(intel->batch);
if (brw->gs.prog_bo) {
BEGIN_BATCH(7);
OUT_BATCH(CMD_3D_GS_STATE << 16 | (7 - 2));
@ -69,17 +80,6 @@ upload_gs_state(struct brw_context *brw)
OUT_BATCH(0);
ADVANCE_BATCH();
}
/* Disable all the constant buffers. */
BEGIN_BATCH(5);
OUT_BATCH(CMD_3D_CONSTANT_GS_STATE << 16 | (5 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(intel->batch);
}
const struct brw_tracked_state gen6_gs_state = {

30
src/mesa/drivers/dri/i965/gen6_vs_state.c
View file

@ -46,21 +46,6 @@ upload_vs_state(struct brw_context *brw)
drm_intel_bo *constant_bo;
int i;
BEGIN_BATCH(6);
OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2));
OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) |
(brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
OUT_BATCH(0); /* scratch space base offset */
OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
(brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
(0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
OUT_BATCH((0 << GEN6_VS_MAX_THREADS_SHIFT) |
GEN6_VS_STATISTICS_ENABLE);
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(intel->batch);
if (vp->use_const_buffer || nr_params == 0) {
/* Disable the push constant buffers. */
BEGIN_BATCH(5);
@ -106,6 +91,21 @@ upload_vs_state(struct brw_context *brw)
}
intel_batchbuffer_emit_mi_flush(intel->batch);
BEGIN_BATCH(6);
OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2));
OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) |
(brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
OUT_BATCH(0); /* scratch space base offset */
OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
(brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
(0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
OUT_BATCH((0 << GEN6_VS_MAX_THREADS_SHIFT) |
GEN6_VS_STATISTICS_ENABLE);
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(intel->batch);
}
const struct brw_tracked_state gen6_vs_state = {

86
src/mesa/drivers/dri/i965/gen6_wm_state.c
View file

@ -47,6 +47,49 @@ upload_wm_state(struct brw_context *brw)
int i;
uint32_t dw2, dw4, dw5, dw6;
if (fp->use_const_buffer || nr_params == 0) {
/* Disable the push constant buffers. */
BEGIN_BATCH(5);
OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 | (5 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
/* Updates the ParamaterValues[i] pointers for all parameters of the
* basic type of PROGRAM_STATE_VAR.
*/
_mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
constant_bo = drm_intel_bo_alloc(intel->bufmgr, "WM constant_bo",
nr_params * 4 * sizeof(float),
4096);
intel_bo_map_gtt_preferred(intel, constant_bo, GL_TRUE);
for (i = 0; i < nr_params; i++) {
memcpy((char *)constant_bo->virtual + i * 4 * sizeof(float),
fp->program.Base.Parameters->ParameterValues[i],
4 * sizeof(float));
}
intel_bo_unmap_gtt_preferred(intel, constant_bo);
BEGIN_BATCH(5);
OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 |
GEN6_CONSTANT_BUFFER_0_ENABLE |
(5 - 2));
OUT_RELOC(constant_bo,
I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */
ALIGN(nr_params, 2) / 2 - 1);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
drm_intel_bo_unreference(constant_bo);
}
intel_batchbuffer_emit_mi_flush(intel->batch);
dw2 = dw4 = dw5 = dw6 = 0;
dw4 |= GEN6_WM_STATISTICS_ENABLE;
dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
@ -103,49 +146,6 @@ upload_wm_state(struct brw_context *brw)
ADVANCE_BATCH();
intel_batchbuffer_emit_mi_flush(intel->batch);
if (fp->use_const_buffer || nr_params == 0) {
/* Disable the push constant buffers. */
BEGIN_BATCH(5);
OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 | (5 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
} else {
/* Updates the ParamaterValues[i] pointers for all parameters of the
* basic type of PROGRAM_STATE_VAR.
*/
_mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
constant_bo = drm_intel_bo_alloc(intel->bufmgr, "WM constant_bo",
nr_params * 4 * sizeof(float),
4096);
intel_bo_map_gtt_preferred(intel, constant_bo, GL_TRUE);
for (i = 0; i < nr_params; i++) {
memcpy((char *)constant_bo->virtual + i * 4 * sizeof(float),
fp->program.Base.Parameters->ParameterValues[i],
4 * sizeof(float));
}
intel_bo_unmap_gtt_preferred(intel, constant_bo);
BEGIN_BATCH(5);
OUT_BATCH(CMD_3D_CONSTANT_PS_STATE << 16 |
GEN6_CONSTANT_BUFFER_0_ENABLE |
(5 - 2));
OUT_RELOC(constant_bo,
I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */
ALIGN(nr_params, 2) / 2 - 1);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
drm_intel_bo_unreference(constant_bo);
}
intel_batchbuffer_emit_mi_flush(intel->batch);
}
const struct brw_tracked_state gen6_wm_state = {