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radeonsi: remove the unused cs parameter from radeon_set_uconfig_reg

Browse source 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13015>
This commit is contained in:
Marek Olšák 2021-09-23 07:17:58 -04:00 • committed by Marge Bot
parent f4ece6cf12
commit 0763bfdb95
7 changed files with 50 additions and 50 deletions
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14
src/gallium/drivers/radeonsi/si_build_pm4.h
View file

@ -122,24 +122,24 @@
radeon_emit(value); \
} while (0)
#define radeon_set_uconfig_reg_seq(cs, reg, num, perfctr) do { \
#define radeon_set_uconfig_reg_seq(reg, num, perfctr) do { \
SI_CHECK_SHADOWED_REGS(reg, num); \
assert((reg) >= CIK_UCONFIG_REG_OFFSET && (reg) < CIK_UCONFIG_REG_END); \
radeon_emit(PKT3(PKT3_SET_UCONFIG_REG, num, perfctr)); \
radeon_emit(((reg) - CIK_UCONFIG_REG_OFFSET) >> 2); \
} while (0)
#define radeon_set_uconfig_reg(cs, reg, value) do { \
radeon_set_uconfig_reg_seq(cs, reg, 1, false); \
#define radeon_set_uconfig_reg(reg, value) do { \
radeon_set_uconfig_reg_seq(reg, 1, false); \
radeon_emit(value); \
} while (0)
#define radeon_set_uconfig_reg_perfctr(cs, reg, value) do { \
radeon_set_uconfig_reg_seq(cs, reg, 1, true); \
#define radeon_set_uconfig_reg_perfctr(reg, value) do { \
radeon_set_uconfig_reg_seq(reg, 1, true); \
radeon_emit(value); \
} while (0)
#define radeon_set_uconfig_reg_idx(cs, screen, chip_class, reg, idx, value) do { \
#define radeon_set_uconfig_reg_idx(screen, chip_class, reg, idx, value) do { \
SI_CHECK_SHADOWED_REGS(reg, 1); \
assert((reg) >= CIK_UCONFIG_REG_OFFSET && (reg) < CIK_UCONFIG_REG_END); \
assert((idx) != 0); \
@ -273,7 +273,7 @@
unsigned __value = val; \
if (((sctx->tracked_regs.reg_saved >> (reg)) & 0x1) != 0x1 || \
sctx->tracked_regs.reg_value[reg] != __value) { \
radeon_set_uconfig_reg(cs, offset, __value); \
radeon_set_uconfig_reg(offset, __value); \
sctx->tracked_regs.reg_saved |= 0x1ull << (reg); \
sctx->tracked_regs.reg_value[reg] = __value; \
} \

4
src/gallium/drivers/radeonsi/si_compute.c
View file

@ -410,7 +410,7 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf
if (sctx->border_color_buffer) {
uint64_t bc_va = sctx->border_color_buffer->gpu_address;
radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2, false);
radeon_set_uconfig_reg_seq(R_030E00_TA_CS_BC_BASE_ADDR, 2, false);
radeon_emit(bc_va >> 8); /* R_030E00_TA_CS_BC_BASE_ADDR */
radeon_emit(S_030E04_ADDRESS(bc_va >> 40)); /* R_030E04_TA_CS_BC_BASE_ADDR_HI */
}
@ -421,7 +421,7 @@ void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf
*/
if (sctx->chip_class >= GFX9 &&
(cs != &sctx->gfx_cs || !sctx->screen->info.has_graphics)) {
radeon_set_uconfig_reg(cs, R_0301EC_CP_COHER_START_DELAY,
radeon_set_uconfig_reg(R_0301EC_CP_COHER_START_DELAY,
sctx->chip_class >= GFX10 ? 0x20 : 0);
}

18
src/gallium/drivers/radeonsi/si_perfcounter.c
View file

@ -81,7 +81,7 @@ static void si_pc_emit_instance(struct si_context *sctx, int se, int instance)
}
radeon_begin(cs);
radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, value);
radeon_set_uconfig_reg(R_030800_GRBM_GFX_INDEX, value);
radeon_end();
}
@ -90,7 +90,7 @@ static void si_pc_emit_shaders(struct si_context *sctx, unsigned shaders)
struct radeon_cmdbuf *cs = &sctx->gfx_cs;
radeon_begin(cs);
radeon_set_uconfig_reg_seq(cs, R_036780_SQ_PERFCOUNTER_CTRL, 2, false);
radeon_set_uconfig_reg_seq(R_036780_SQ_PERFCOUNTER_CTRL, 2, false);
radeon_emit(shaders & 0x7f);
radeon_emit(0xffffffff);
radeon_end();
@ -112,12 +112,12 @@ static void si_pc_emit_select(struct si_context *sctx, struct ac_pc_block *block
radeon_begin(cs);
for (idx = 0; idx < count; ++idx) {
radeon_set_uconfig_reg_seq(cs, regs->select0[idx], 1, false);
radeon_set_uconfig_reg_seq(regs->select0[idx], 1, false);
radeon_emit(selectors[idx] | regs->select_or);
}
for (idx = 0; idx < regs->num_spm_counters; idx++) {
radeon_set_uconfig_reg_seq(cs, regs->select1[idx], 1, false);
radeon_set_uconfig_reg_seq(regs->select1[idx], 1, false);
radeon_emit(0);
}
@ -132,11 +132,11 @@ static void si_pc_emit_start(struct si_context *sctx, struct si_resource *buffer
COPY_DATA_IMM, NULL, 1);
radeon_begin(cs);
radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
radeon_set_uconfig_reg(R_036020_CP_PERFMON_CNTL,
S_036020_PERFMON_STATE(V_036020_CP_PERFMON_STATE_DISABLE_AND_RESET));
radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(EVENT_TYPE(V_028A90_PERFCOUNTER_START) | EVENT_INDEX(0));
radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
radeon_set_uconfig_reg(R_036020_CP_PERFMON_CNTL,
S_036020_PERFMON_STATE(V_036020_CP_PERFMON_STATE_START_COUNTING));
radeon_end();
}
@ -157,7 +157,7 @@ static void si_pc_emit_stop(struct si_context *sctx, struct si_resource *buffer,
radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(EVENT_TYPE(V_028A90_PERFCOUNTER_STOP) | EVENT_INDEX(0));
radeon_set_uconfig_reg(
cs, R_036020_CP_PERFMON_CNTL,
R_036020_CP_PERFMON_CNTL,
S_036020_PERFMON_STATE(V_036020_CP_PERFMON_STATE_STOP_COUNTING) | S_036020_PERFMON_SAMPLE_ENABLE(1));
radeon_end();
}
@ -225,10 +225,10 @@ void si_inhibit_clockgating(struct si_context *sctx, struct radeon_cmdbuf *cs, b
radeon_begin(&sctx->gfx_cs);
if (sctx->chip_class >= GFX10) {
radeon_set_uconfig_reg(cs, R_037390_RLC_PERFMON_CLK_CNTL,
radeon_set_uconfig_reg(R_037390_RLC_PERFMON_CLK_CNTL,
S_037390_PERFMON_CLOCK_STATE(inhibit));
} else if (sctx->chip_class >= GFX8) {
radeon_set_uconfig_reg(cs, R_0372FC_RLC_PERFMON_CLK_CNTL,
radeon_set_uconfig_reg(R_0372FC_RLC_PERFMON_CLK_CNTL,
S_0372FC_PERFMON_CLOCK_STATE(inhibit));
}
radeon_end();

36
src/gallium/drivers/radeonsi/si_sqtt.c
View file

@ -94,7 +94,7 @@ si_emit_thread_trace_start(struct si_context* sctx,
continue;
/* Target SEx and SH0. */
radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
radeon_set_uconfig_reg(R_030800_GRBM_GFX_INDEX,
S_030800_SE_INDEX(se) |
S_030800_SH_INDEX(0) |
S_030800_INSTANCE_BROADCAST_WRITES(1));
@ -141,15 +141,15 @@ si_emit_thread_trace_start(struct si_context* sctx,
sctx->chip_class >= GFX10_3 ? 4 : 0));
} else {
/* Order seems important for the following 4 registers. */
radeon_set_uconfig_reg(cs, R_030CDC_SQ_THREAD_TRACE_BASE2,
radeon_set_uconfig_reg(R_030CDC_SQ_THREAD_TRACE_BASE2,
S_030CDC_ADDR_HI(shifted_va >> 32));
radeon_set_uconfig_reg(cs, R_030CC0_SQ_THREAD_TRACE_BASE, shifted_va);
radeon_set_uconfig_reg(R_030CC0_SQ_THREAD_TRACE_BASE, shifted_va);
radeon_set_uconfig_reg(cs, R_030CC4_SQ_THREAD_TRACE_SIZE,
radeon_set_uconfig_reg(R_030CC4_SQ_THREAD_TRACE_SIZE,
S_030CC4_SIZE(shifted_size));
radeon_set_uconfig_reg(cs, R_030CD4_SQ_THREAD_TRACE_CTRL,
radeon_set_uconfig_reg(R_030CD4_SQ_THREAD_TRACE_CTRL,
S_030CD4_RESET_BUFFER(1));
uint32_t thread_trace_mask = S_030CC8_CU_SEL(first_active_cu) |
@ -160,28 +160,28 @@ si_emit_thread_trace_start(struct si_context* sctx,
S_030CC8_SPI_STALL_EN(1) |
S_030CC8_SQ_STALL_EN(1);
radeon_set_uconfig_reg(cs, R_030CC8_SQ_THREAD_TRACE_MASK,
radeon_set_uconfig_reg(R_030CC8_SQ_THREAD_TRACE_MASK,
thread_trace_mask);
/* Trace all tokens and registers. */
radeon_set_uconfig_reg(cs, R_030CCC_SQ_THREAD_TRACE_TOKEN_MASK,
radeon_set_uconfig_reg(R_030CCC_SQ_THREAD_TRACE_TOKEN_MASK,
S_030CCC_TOKEN_MASK(0xbfff) |
S_030CCC_REG_MASK(0xff) |
S_030CCC_REG_DROP_ON_STALL(0));
/* Enable SQTT perf counters for all CUs. */
radeon_set_uconfig_reg(cs, R_030CD0_SQ_THREAD_TRACE_PERF_MASK,
radeon_set_uconfig_reg(R_030CD0_SQ_THREAD_TRACE_PERF_MASK,
S_030CD0_SH0_MASK(0xffff) |
S_030CD0_SH1_MASK(0xffff));
radeon_set_uconfig_reg(cs, R_030CE0_SQ_THREAD_TRACE_TOKEN_MASK2, 0xffffffff);
radeon_set_uconfig_reg(R_030CE0_SQ_THREAD_TRACE_TOKEN_MASK2, 0xffffffff);
radeon_set_uconfig_reg(cs, R_030CEC_SQ_THREAD_TRACE_HIWATER,
radeon_set_uconfig_reg(R_030CEC_SQ_THREAD_TRACE_HIWATER,
S_030CEC_HIWATER(4));
if (sctx->chip_class == GFX9) {
/* Reset thread trace status errors. */
radeon_set_uconfig_reg(cs, R_030CE8_SQ_THREAD_TRACE_STATUS,
radeon_set_uconfig_reg(R_030CE8_SQ_THREAD_TRACE_STATUS,
S_030CE8_UTC_ERROR(0));
}
@ -202,13 +202,13 @@ si_emit_thread_trace_start(struct si_context* sctx,
thread_trace_mode |= S_030CD8_TC_PERF_EN(1);
}
radeon_set_uconfig_reg(cs, R_030CD8_SQ_THREAD_TRACE_MODE,
radeon_set_uconfig_reg(R_030CD8_SQ_THREAD_TRACE_MODE,
thread_trace_mode);
}
}
/* Restore global broadcasting. */
radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
radeon_set_uconfig_reg(R_030800_GRBM_GFX_INDEX,
S_030800_SE_BROADCAST_WRITES(1) |
S_030800_SH_BROADCAST_WRITES(1) |
S_030800_INSTANCE_BROADCAST_WRITES(1));
@ -308,7 +308,7 @@ si_emit_thread_trace_stop(struct si_context *sctx,
radeon_begin(cs);
/* Target SEi and SH0. */
radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
radeon_set_uconfig_reg(R_030800_GRBM_GFX_INDEX,
S_030800_SE_INDEX(se) |
S_030800_SH_INDEX(0) |
S_030800_INSTANCE_BROADCAST_WRITES(1));
@ -337,7 +337,7 @@ si_emit_thread_trace_stop(struct si_context *sctx,
radeon_emit(4); /* poll interval */
} else {
/* Disable the thread trace mode. */
radeon_set_uconfig_reg(cs, R_030CD8_SQ_THREAD_TRACE_MODE,
radeon_set_uconfig_reg(R_030CD8_SQ_THREAD_TRACE_MODE,
S_030CD8_MODE(0));
/* Wait for thread trace completion. */
@ -356,7 +356,7 @@ si_emit_thread_trace_stop(struct si_context *sctx,
/* Restore global broadcasting. */
radeon_begin_again(cs);
radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
radeon_set_uconfig_reg(R_030800_GRBM_GFX_INDEX,
S_030800_SE_BROADCAST_WRITES(1) |
S_030800_SH_BROADCAST_WRITES(1) |
S_030800_INSTANCE_BROADCAST_WRITES(1));
@ -735,7 +735,7 @@ si_emit_thread_trace_userdata(struct si_context* sctx,
/* Without the perfctr bit the CP might not always pass the
* write on correctly. */
radeon_set_uconfig_reg_seq(cs, R_030D08_SQ_THREAD_TRACE_USERDATA_2, count, sctx->chip_class >= GFX10);
radeon_set_uconfig_reg_seq(R_030D08_SQ_THREAD_TRACE_USERDATA_2, count, sctx->chip_class >= GFX10);
radeon_emit_array(dwords, count);
@ -760,7 +760,7 @@ si_emit_spi_config_cntl(struct si_context* sctx,
if (sctx->chip_class >= GFX10)
spi_config_cntl |= S_031100_PS_PKR_PRIORITY_CNTL(3);
radeon_set_uconfig_reg(cs, R_031100_SPI_CONFIG_CNTL, spi_config_cntl);
radeon_set_uconfig_reg(R_031100_SPI_CONFIG_CNTL, spi_config_cntl);
} else {
/* SPI_CONFIG_CNTL is a protected register on GFX6-GFX8. */
radeon_set_privileged_config_reg(cs, R_009100_SPI_CONFIG_CNTL,

12
src/gallium/drivers/radeonsi/si_state_draw.cpp
View file

@ -1161,7 +1161,7 @@ static void si_emit_ia_multi_vgt_param(struct si_context *sctx,
radeon_begin(cs);
if (GFX_VERSION == GFX9)
radeon_set_uconfig_reg_idx(cs, sctx->screen, GFX_VERSION,
radeon_set_uconfig_reg_idx(sctx->screen, GFX_VERSION,
R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
else if (GFX_VERSION >= GFX7)
radeon_set_context_reg_idx(R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
@ -1217,7 +1217,7 @@ static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches)
struct radeon_cmdbuf *cs = &sctx->gfx_cs;
radeon_begin(cs);
radeon_set_uconfig_reg(cs, R_03096C_GE_CNTL, ge_cntl);
radeon_set_uconfig_reg(R_03096C_GE_CNTL, ge_cntl);
radeon_end();
sctx->last_multi_vgt_param = ge_cntl;
}
@ -1245,9 +1245,9 @@ static void si_emit_draw_registers(struct si_context *sctx,
unsigned vgt_prim = si_conv_pipe_prim(prim);
if (GFX_VERSION >= GFX10)
radeon_set_uconfig_reg(cs, R_030908_VGT_PRIMITIVE_TYPE, vgt_prim);
radeon_set_uconfig_reg(R_030908_VGT_PRIMITIVE_TYPE, vgt_prim);
else if (GFX_VERSION >= GFX7)
radeon_set_uconfig_reg_idx(cs, sctx->screen, GFX_VERSION, R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
radeon_set_uconfig_reg_idx(sctx->screen, GFX_VERSION, R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
else
radeon_set_config_reg(R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);
@ -1257,7 +1257,7 @@ static void si_emit_draw_registers(struct si_context *sctx,
/* Primitive restart. */
if (primitive_restart != sctx->last_primitive_restart_en) {
if (GFX_VERSION >= GFX9)
radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN, primitive_restart);
radeon_set_uconfig_reg(R_03092C_VGT_MULTI_PRIM_IB_RESET_EN, primitive_restart);
else
radeon_set_context_reg(R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, primitive_restart);
@ -1343,7 +1343,7 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw
}
if (GFX_VERSION >= GFX9) {
radeon_set_uconfig_reg_idx(cs, sctx->screen, GFX_VERSION,
radeon_set_uconfig_reg_idx(sctx->screen, GFX_VERSION,
R_03090C_VGT_INDEX_TYPE, 2, index_type);
} else {
radeon_emit(PKT3(PKT3_INDEX_TYPE, 0, 0));

14
src/gallium/drivers/radeonsi/si_state_shaders.c
View file

@ -3644,11 +3644,11 @@ bool si_update_gs_ring_buffers(struct si_context *sctx)
/* Set the GS registers. */
if (sctx->esgs_ring) {
assert(sctx->chip_class <= GFX8);
radeon_set_uconfig_reg(cs, R_030900_VGT_ESGS_RING_SIZE,
radeon_set_uconfig_reg(R_030900_VGT_ESGS_RING_SIZE,
sctx->esgs_ring->width0 / 256);
}
if (sctx->gsvs_ring) {
radeon_set_uconfig_reg(cs, R_030904_VGT_GSVS_RING_SIZE,
radeon_set_uconfig_reg(R_030904_VGT_GSVS_RING_SIZE,
sctx->gsvs_ring->width0 / 256);
}
radeon_end();
@ -3910,17 +3910,17 @@ void si_init_tess_factor_ring(struct si_context *sctx)
/* Set tessellation registers. */
radeon_begin(cs);
radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
radeon_set_uconfig_reg(R_030938_VGT_TF_RING_SIZE,
S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE, factor_va >> 8);
radeon_set_uconfig_reg(R_030940_VGT_TF_MEMORY_BASE, factor_va >> 8);
if (sctx->chip_class >= GFX10) {
radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
radeon_set_uconfig_reg(R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
S_030984_BASE_HI(factor_va >> 40));
} else if (sctx->chip_class == GFX9) {
radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
radeon_set_uconfig_reg(R_030944_VGT_TF_MEMORY_BASE_HI,
S_030944_BASE_HI(factor_va >> 40));
}
radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
radeon_set_uconfig_reg(R_03093C_VGT_HS_OFFCHIP_PARAM,
sctx->screen->vgt_hs_offchip_param);
radeon_end();
return;

2
src/gallium/drivers/radeonsi/si_state_streamout.c
View file

@ -284,7 +284,7 @@ static void si_flush_vgt_streamout(struct si_context *sctx)
/* The register is at different places on different ASICs. */
if (sctx->chip_class >= GFX7) {
reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
radeon_set_uconfig_reg(cs, reg_strmout_cntl, 0);
radeon_set_uconfig_reg(reg_strmout_cntl, 0);
} else {
reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
radeon_set_config_reg(reg_strmout_cntl, 0);