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pan/mdg: Type CSEL with a NIR pass
As an off-shoot of trying to delete modifiers (and nir_register) from NIR, I'd like to get rid of some of the modifier NIR silliness that Midgard is doing. The CSEL type selection heuristic at NIR->MIR time is peak backend silly, so replace it with nir_gather_ssa_types. Small win on shader-db. I didn't investigate much, but this matches my intution for how this patch would perform: very small instruction/cycle count improvements due to slightly better decisions around modifiers, more substantial space savings due to more float constants getting inlined. total instructions in shared programs: 1518422 -> 1518414 (<.01%) instructions in affected programs: 1914 -> 1906 (-0.42%) helped: 8 HURT: 0 Instructions are helped. total bundles in shared programs: 646941 -> 646937 (<.01%) bundles in affected programs: 344 -> 340 (-1.16%) helped: 4 HURT: 0 Bundles are helped. total quadwords in shared programs: 1134727 -> 1134324 (-0.04%) quadwords in affected programs: 66752 -> 66349 (-0.60%) helped: 351 HURT: 54 Quadwords are helped. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Italo Nicola <italonicola@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23769>
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311bfd0623
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4 changed files with 53 additions and 47 deletions
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@ -35,6 +35,7 @@ libpanfrost_midgard_files = files(
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'mir_promote_uniforms.c',
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'mir_squeeze.c',
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'midgard_nir_lower_image_bitsize.c',
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'midgard_nir_type_csel.c',
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'midgard_opt_copy_prop.c',
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'midgard_opt_dce.c',
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'midgard_opt_perspective.c',
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@ -459,6 +459,7 @@ optimise_nir(nir_shader *nir, unsigned quirks, bool is_blend)
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/* Now that booleans are lowered, we can run out late opts */
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NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
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NIR_PASS(progress, nir, midgard_nir_cancel_inot);
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NIR_PASS_V(nir, midgard_nir_type_csel);
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NIR_PASS(progress, nir, nir_copy_prop);
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NIR_PASS(progress, nir, nir_opt_dce);
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@ -697,50 +698,6 @@ mir_copy_src(midgard_instruction *ins, nir_alu_instr *instr, unsigned i,
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}
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}
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/* Midgard features both fcsel and icsel, depending on whether you want int or
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* float modifiers. NIR's csel is typeless, so we want a heuristic to guess if
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* we should emit an int or float csel depending on what modifiers could be
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* placed. In the absense of modifiers, this is probably arbitrary. */
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static bool
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mir_is_bcsel_float(nir_alu_instr *instr)
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{
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nir_op intmods[] = {nir_op_i2i8, nir_op_i2i16, nir_op_i2i32, nir_op_i2i64};
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nir_op floatmods[] = {nir_op_fabs, nir_op_fneg, nir_op_f2f16, nir_op_f2f32,
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nir_op_f2f64};
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nir_op floatdestmods[] = {nir_op_fsat, nir_op_fsat_signed_mali,
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nir_op_fclamp_pos_mali, nir_op_f2f16,
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nir_op_f2f32};
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signed score = 0;
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for (unsigned i = 1; i < 3; ++i) {
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nir_alu_src s = instr->src[i];
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for (unsigned q = 0; q < ARRAY_SIZE(intmods); ++q) {
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if (pan_has_source_mod(&s, intmods[q]))
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score--;
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}
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}
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for (unsigned i = 1; i < 3; ++i) {
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nir_alu_src s = instr->src[i];
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for (unsigned q = 0; q < ARRAY_SIZE(floatmods); ++q) {
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if (pan_has_source_mod(&s, floatmods[q]))
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score++;
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}
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}
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for (unsigned q = 0; q < ARRAY_SIZE(floatdestmods); ++q) {
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nir_dest *dest = &instr->dest.dest;
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if (pan_has_dest_mod(&dest, floatdestmods[q]))
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score++;
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}
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return (score > 0);
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}
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static void
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emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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{
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@ -940,9 +897,10 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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break;
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}
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case nir_op_b32csel: {
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case nir_op_b32csel:
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case nir_op_b32fcsel_mdg: {
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bool mixed = nir_is_non_scalar_swizzle(&instr->src[0], nr_components);
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bool is_float = mir_is_bcsel_float(instr);
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bool is_float = instr->op == nir_op_b32fcsel_mdg;
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op = is_float ? (mixed ? midgard_alu_op_fcsel_v : midgard_alu_op_fcsel)
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: (mixed ? midgard_alu_op_icsel_v : midgard_alu_op_icsel);
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@ -1021,7 +979,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
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for (unsigned i = 0; i < nr_inputs; ++i) {
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unsigned to = i;
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if (instr->op == nir_op_b32csel) {
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if (instr->op == nir_op_b32csel || instr->op == nir_op_b32fcsel_mdg) {
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/* The condition is the first argument; move
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* the other arguments up one to be a binary
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* instruction for Midgard with the condition
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@ -4,4 +4,5 @@
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bool midgard_nir_lower_algebraic_early(nir_shader *shader);
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bool midgard_nir_lower_algebraic_late(nir_shader *shader);
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bool midgard_nir_cancel_inot(nir_shader *shader);
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void midgard_nir_type_csel(nir_shader *shader);
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bool midgard_nir_lower_image_bitsize(nir_shader *shader);
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46
src/panfrost/midgard/midgard_nir_type_csel.c
Normal file
46
src/panfrost/midgard/midgard_nir_type_csel.c
Normal file
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@ -0,0 +1,46 @@
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/*
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* Copyright 2023 Valve Corporation
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* SPDX-License-Identifier: MIT
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*/
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#include "compiler/nir/nir.h"
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#include "compiler/nir/nir_builder.h"
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#include "midgard_nir.h"
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#include "nir_opcodes.h"
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static bool
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pass(nir_builder *b, nir_instr *instr, void *data)
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{
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if (instr->type != nir_instr_type_alu)
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return false;
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nir_alu_instr *alu = nir_instr_as_alu(instr);
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if (alu->op != nir_op_b32csel)
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return false;
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BITSET_WORD *float_types = data;
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assert(alu->dest.dest.is_ssa);
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if (BITSET_TEST(float_types, alu->dest.dest.ssa.index)) {
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alu->op = nir_op_b32fcsel_mdg;
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return true;
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} else {
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return false;
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}
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}
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void
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midgard_nir_type_csel(nir_shader *shader)
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{
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nir_function_impl *impl = nir_shader_get_entrypoint(shader);
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nir_index_ssa_defs(impl);
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BITSET_WORD *float_types =
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calloc(BITSET_WORDS(impl->ssa_alloc), sizeof(BITSET_WORD));
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nir_gather_ssa_types(impl, float_types, NULL);
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nir_shader_instructions_pass(
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shader, pass, nir_metadata_block_index | nir_metadata_dominance,
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float_types);
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free(float_types);
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}
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