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radeonsi: invalidate compute sgprs in si_rebind_buffer

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If we don't tag compute sgpr as dirty they will point to the
ol buffer location.
This fixes arb_compute_shader-dlist with mcbp enabled.

Fixes: 85a6bcca61 ("radeonsi: pass at most 3 images and/or shader buffers via user SGPRs for compute")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8433>
(cherry picked from commit 17f8e56c96)
This commit is contained in:
Pierre-Eric Pelloux-Prayer 2021-01-11 20:40:09 +01:00 • committed by Dylan Baker
parent 8d2bc1e60b
commit 074631dd67
2 changed files with 17 additions and 7 deletions
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2
.pick_status.json
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@ -40,7 +40,7 @@
"description": "radeonsi: invalidate compute sgprs in si_rebind_buffer",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"master_sha": null,
"because_sha": "85a6bcca615f9aae1ffd2a1e790ee5d980e7cc43"
},

22
src/gallium/drivers/radeonsi/si_descriptors.c
View file

@ -1482,11 +1482,12 @@ void si_update_needs_color_decompress_masks(struct si_context *sctx)
/* Reset descriptors of buffer resources after \p buf has been invalidated.
* If buf == NULL, reset all descriptors.
*/
static void si_reset_buffer_resources(struct si_context *sctx, struct si_buffer_resources *buffers,
static bool si_reset_buffer_resources(struct si_context *sctx, struct si_buffer_resources *buffers,
unsigned descriptors_idx, uint64_t slot_mask,
struct pipe_resource *buf, enum radeon_bo_priority priority)
{
struct si_descriptors *descs = &sctx->descriptors[descriptors_idx];
bool noop = true;
uint64_t mask = buffers->enabled_mask & slot_mask;
while (mask) {
@ -1501,8 +1502,10 @@ static void si_reset_buffer_resources(struct si_context *sctx, struct si_buffer_
sctx, si_resource(buffer),
buffers->writable_mask & (1llu << i) ? RADEON_USAGE_READWRITE : RADEON_USAGE_READ,
priority, true);
noop = false;
}
}
return !noop;
}
/* Update all buffer bindings where the buffer is bound, including
@ -1577,11 +1580,15 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
}
if (!buffer || buffer->bind_history & PIPE_BIND_SHADER_BUFFER) {
for (shader = 0; shader < SI_NUM_SHADERS; shader++)
si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
si_const_and_shader_buffer_descriptors_idx(shader),
u_bit_consecutive64(0, SI_NUM_SHADER_BUFFERS), buf,
sctx->const_and_shader_buffers[shader].priority);
for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
if (si_reset_buffer_resources(sctx, &sctx->const_and_shader_buffers[shader],
si_const_and_shader_buffer_descriptors_idx(shader),
u_bit_consecutive64(0, SI_NUM_SHADER_BUFFERS), buf,
sctx->const_and_shader_buffers[shader].priority) &&
shader == PIPE_SHADER_COMPUTE) {
sctx->compute_shaderbuf_sgprs_dirty = true;
}
}
}
if (!buffer || buffer->bind_history & PIPE_BIND_SAMPLER_VIEW) {
@ -1633,6 +1640,9 @@ void si_rebind_buffer(struct si_context *sctx, struct pipe_resource *buf)
radeon_add_to_gfx_buffer_list_check_mem(sctx, si_resource(buffer),
RADEON_USAGE_READWRITE,
RADEON_PRIO_SAMPLER_BUFFER, true);
if (shader == PIPE_SHADER_COMPUTE)
sctx->compute_image_sgprs_dirty = true;
}
}
}