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brw: fix vecN rebuilds

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When loading a 64bit address from the push constants, we'll load a
vec2, so we need to allocate 2 GRFs and MOV each component.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11831
Fixes: 339630ab05 ("brw: enable A64 loads source rematerialization")
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31010>
(cherry picked from commit 45377dc5c4)
This commit is contained in:
Lionel Landwerlin 2024-09-03 23:21:50 +03:00 • committed by Eric Engestrom
parent 00c6a487d5
commit 0722d2a0ae
2 changed files with 27 additions and 10 deletions
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2
.pick_status.json
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@ -4,7 +4,7 @@
"description": "brw: fix vecN rebuilds",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "339630ab05abcaf11a9f67b2dd42ef793d2f689a",
"notes": null

35
src/intel/compiler/brw_fs_nir.cpp
View file

@ -4797,6 +4797,7 @@ try_rebuild_source(nir_to_brw_state &ntb, const brw::fs_builder &bld,
{
/* Create a build at the location of the resource_intel intrinsic */
fs_builder ubld = bld.exec_all().group(8 * reg_unit(ntb.devinfo), 0);
const unsigned grf_size = REG_SIZE * reg_unit(ntb.devinfo);
struct rebuild_resource resources = {};
resources.idx = 0;
@ -4975,10 +4976,18 @@ try_rebuild_source(nir_to_brw_state &ntb, const brw::fs_builder &bld,
unsigned base_offset = nir_intrinsic_base(intrin);
unsigned load_offset = nir_src_as_uint(intrin->src[0]);
brw_reg src = brw_uniform_reg(base_offset / 4,
brw_type_with_size(BRW_TYPE_D, intrin->def.bit_size));
src.offset = load_offset + base_offset % 4;
ubld.MOV(src, &ntb.resource_insts[def->index]);
enum brw_reg_type type =
brw_type_with_size(BRW_TYPE_D, intrin->def.bit_size);
brw_reg dst_data = ubld.vgrf(type, intrin->def.num_components);
for (unsigned i = 0; i < intrin->def.num_components; i++) {
brw_reg src = brw_uniform_reg(base_offset / 4, type);
src.offset = load_offset + base_offset % 4 + i * intrin->def.bit_size / 8;
fs_inst *inst = ubld.MOV(byte_offset(dst_data, i * grf_size), src);
if (i == 0)
ntb.resource_insts[def->index] = inst;
}
break;
}
@ -4986,11 +4995,19 @@ try_rebuild_source(nir_to_brw_state &ntb, const brw::fs_builder &bld,
assert(ntb.s.stage == MESA_SHADER_MESH ||
ntb.s.stage == MESA_SHADER_TASK);
const task_mesh_thread_payload &payload = ntb.s.task_mesh_payload();
brw_reg data = retype(
offset(payload.inline_parameter, 1,
nir_intrinsic_align_offset(intrin)),
brw_type_with_size(BRW_TYPE_D, intrin->def.bit_size));
ubld.MOV(data, &ntb.resource_insts[def->index]);
enum brw_reg_type type =
brw_type_with_size(BRW_TYPE_D, intrin->def.bit_size);
brw_reg dst_data = ubld.vgrf(type, intrin->def.num_components);
for (unsigned i = 0; i < intrin->def.num_components; i++) {
brw_reg src = retype(
offset(payload.inline_parameter, 1,
nir_intrinsic_align_offset(intrin) + i * intrin->def.bit_size / 8),
brw_type_with_size(BRW_TYPE_D, intrin->def.bit_size));
fs_inst *inst = ubld.MOV(byte_offset(dst_data, i * grf_size), src);
if (i == 0)
ntb.resource_insts[def->index] = inst;
}
break;
}