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intel/brw: Remove F16TO32 and F32TO16 opcodes

Browse source 
These are done with MOVs and appropriate types in Gfx9+.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27691>
This commit is contained in:
Caio Oliveira 2024-02-17 21:55:18 -08:00 • committed by Marge Bot
parent 866a2f88df
commit 071e9f49f1
8 changed files with 7 additions and 79 deletions
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2
src/intel/compiler/brw_eu.c
View file

@ -624,8 +624,6 @@ static const struct opcode_desc opcode_descs[] = {
{ BRW_OPCODE_CMPN, 113, "cmpn", 2, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_CSEL, 18, "csel", 3, 1, GFX_GE(GFX8) & GFX_LT(GFX12) },
{ BRW_OPCODE_CSEL, 114, "csel", 3, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_F32TO16, 19, "f32to16", 1, 1, GFX7 | GFX75 },
{ BRW_OPCODE_F16TO32, 20, "f16to32", 1, 1, GFX7 | GFX75 },
{ BRW_OPCODE_BFREV, 23, "bfrev", 1, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },
{ BRW_OPCODE_BFREV, 119, "bfrev", 1, 1, GFX_GE(GFX12) },
{ BRW_OPCODE_BFE, 24, "bfe", 3, 1, GFX_GE(GFX7) & GFX_LT(GFX12) },

2
src/intel/compiler/brw_eu_defines.h
View file

@ -195,8 +195,6 @@ enum opcode {
BRW_OPCODE_CMP,
BRW_OPCODE_CMPN,
BRW_OPCODE_CSEL, /**< Gfx8+ */
BRW_OPCODE_F32TO16, /**< Gfx7 only */
BRW_OPCODE_F16TO32, /**< Gfx7 only */
BRW_OPCODE_BFREV, /**< Gfx7+ */
BRW_OPCODE_BFE, /**< Gfx7+ */
BRW_OPCODE_BFI1, /**< Gfx7+ */

30
src/intel/compiler/brw_fs_builder.h
View file

@ -664,36 +664,6 @@ namespace brw {
#undef ALU2_ACC
#undef ALU2
#undef ALU1
instruction *
F32TO16(const dst_reg &dst, const src_reg &src) const
{
assert(dst.type == BRW_REGISTER_TYPE_HF);
assert(src.type == BRW_REGISTER_TYPE_F);
if (shader->devinfo->ver >= 8) {
return MOV(dst, src);
} else {
assert(shader->devinfo->ver == 7);
return emit(BRW_OPCODE_F32TO16,
retype(dst, BRW_REGISTER_TYPE_W), src);
}
}
instruction *
F16TO32(const dst_reg &dst, const src_reg &src) const
{
assert(dst.type == BRW_REGISTER_TYPE_F);
assert(src.type == BRW_REGISTER_TYPE_HF);
if (shader->devinfo->ver >= 8) {
return MOV(dst, src);
} else {
assert(shader->devinfo->ver == 7);
return emit(BRW_OPCODE_F16TO32,
dst, retype(src, BRW_REGISTER_TYPE_W));
}
}
/** @} */
/**

4
src/intel/compiler/brw_fs_lower_pack.cpp
View file

@ -65,8 +65,8 @@ brw_fs_lower_pack(fs_visitor &s)
ibld.MOV(subscript(dst, BRW_REGISTER_TYPE_UW, i),
brw_imm_uw(half));
} else {
ibld.F32TO16(subscript(dst, BRW_REGISTER_TYPE_HF, i),
inst->src[i]);
ibld.MOV(subscript(dst, BRW_REGISTER_TYPE_HF, i),
inst->src[i]);
}
}
break;

16
src/intel/compiler/brw_fs_lower_simd_width.cpp
View file

@ -11,12 +11,6 @@ using namespace brw;
static bool
is_mixed_float_with_fp32_dst(const fs_inst *inst)
{
/* This opcode sometimes uses :W type on the source even if the operand is
* a :HF, because in gfx7 there is no support for :HF, and thus it uses :W.
*/
if (inst->opcode == BRW_OPCODE_F16TO32)
return true;
if (inst->dst.type != BRW_REGISTER_TYPE_F)
return false;
@ -31,14 +25,6 @@ is_mixed_float_with_fp32_dst(const fs_inst *inst)
static bool
is_mixed_float_with_packed_fp16_dst(const fs_inst *inst)
{
/* This opcode sometimes uses :W type on the destination even if the
* destination is a :HF, because in gfx7 there is no support for :HF, and
* thus it uses :W.
*/
if (inst->opcode == BRW_OPCODE_F32TO16 &&
inst->dst.stride == 1)
return true;
if (inst->dst.type != BRW_REGISTER_TYPE_HF ||
inst->dst.stride != 1)
return false;
@ -378,8 +364,6 @@ brw_fs_get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst)
case BRW_OPCODE_ROL:
case BRW_OPCODE_CMPN:
case BRW_OPCODE_CSEL:
case BRW_OPCODE_F32TO16:
case BRW_OPCODE_F16TO32:
case BRW_OPCODE_BFREV:
case BRW_OPCODE_BFE:
case BRW_OPCODE_ADD:

10
src/intel/compiler/brw_fs_nir.cpp
View file

@ -1080,7 +1080,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr,
bld.exec_all().emit(SHADER_OPCODE_RND_MODE, bld.null_reg_ud(), brw_imm_d(rnd));
assert(type_sz(op[0].type) < 8); /* brw_nir_lower_conversions */
inst = bld.F32TO16(result, op[0]);
inst = bld.MOV(result, op[0]);
break;
}
@ -1605,8 +1605,8 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr,
retype(op[0], BRW_REGISTER_TYPE_UD),
brw_imm_ud(0x80000000));
/* Do the actual F32 -> F16 -> F32 conversion */
bld.F32TO16(tmp16, op[0]);
bld.F16TO32(tmp32, tmp16);
bld.MOV(tmp16, op[0]);
bld.MOV(tmp32, tmp16);
/* Select that or zero based on normal status */
inst = bld.SEL(result, zero, tmp32);
inst->predicate = BRW_PREDICATE_NORMAL;
@ -1641,14 +1641,14 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr,
assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 & execution_mode);
FALLTHROUGH;
case nir_op_unpack_half_2x16_split_x:
inst = bld.F16TO32(result, subscript(op[0], BRW_REGISTER_TYPE_HF, 0));
inst = bld.MOV(result, subscript(op[0], BRW_REGISTER_TYPE_HF, 0));
break;
case nir_op_unpack_half_2x16_split_y_flush_to_zero:
assert(FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP16 & execution_mode);
FALLTHROUGH;
case nir_op_unpack_half_2x16_split_y:
inst = bld.F16TO32(result, subscript(op[0], BRW_REGISTER_TYPE_HF, 1));
inst = bld.MOV(result, subscript(op[0], BRW_REGISTER_TYPE_HF, 1));
break;
case nir_op_pack_64_2x32_split:

9
src/intel/compiler/brw_ir_performance.cpp
View file

@ -286,7 +286,6 @@ namespace {
case BRW_OPCODE_DIM:
case BRW_OPCODE_ASR:
case BRW_OPCODE_CMPN:
case BRW_OPCODE_F16TO32:
case BRW_OPCODE_BFREV:
case BRW_OPCODE_BFI1:
case BRW_OPCODE_AVG:
@ -382,14 +381,6 @@ namespace {
0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0);
}
case BRW_OPCODE_F32TO16:
if (devinfo->ver >= 11)
return calculate_desc(info, EU_UNIT_FPU, 0, 4, 0, 0, 4,
0, 10, 6 /* XXX */, 14 /* XXX */, 0, 0);
else
return calculate_desc(info, EU_UNIT_FPU, 0, 4, 0, 0, 4,
0, 8, 4 /* XXX */, 12 /* XXX */, 0, 0);
case BRW_OPCODE_DP4:
case BRW_OPCODE_DPH:
case BRW_OPCODE_DP3:

13
src/intel/compiler/brw_shader.cpp
View file

@ -155,15 +155,6 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op)
if (devinfo->ver >= 6 && op == BRW_OPCODE_DO)
return "do";
/* The following conversion opcodes doesn't exist on Gfx8+, but we use
* then to mark that we want to do the conversion.
*/
if (devinfo->ver > 7 && op == BRW_OPCODE_F32TO16)
return "f32to16";
if (devinfo->ver > 7 && op == BRW_OPCODE_F16TO32)
return "f16to32";
/* DPAS instructions may transiently exist on platforms that do not
* support DPAS. They will eventually be lowered, but in the meantime it
* must be possible to query the instruction name.
@ -945,8 +936,6 @@ backend_instruction::can_do_saturate() const
case BRW_OPCODE_DP4:
case BRW_OPCODE_DPH:
case BRW_OPCODE_DP4A:
case BRW_OPCODE_F16TO32:
case BRW_OPCODE_F32TO16:
case BRW_OPCODE_LINE:
case BRW_OPCODE_LRP:
case BRW_OPCODE_MAC:
@ -994,8 +983,6 @@ backend_instruction::can_do_cmod() const
case BRW_OPCODE_DP3:
case BRW_OPCODE_DP4:
case BRW_OPCODE_DPH:
case BRW_OPCODE_F16TO32:
case BRW_OPCODE_F32TO16:
case BRW_OPCODE_FRC:
case BRW_OPCODE_LINE:
case BRW_OPCODE_LRP: