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brw: Split brw_postprocess_nir() into two pieces

Browse source 
brw_postprocess_nir contains a lot of stuff these days.  The first part
does a bunch of lowering and cleanup optimizations in SSA form.  The
second part does some post-optimization lowering and the out-of-SSA
conversion.

We may want to do additional work before the post-optimization/post-SSA
phase.  Splitting this allows us to insert such tasks in the "middle".

For convenience, brw_postprocess_nir() becomes a wrapper which invokes
both parts, so callers can continue working as they did until they have
a reason to do otherwise.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36750>
This commit is contained in:
Kenneth Graunke 2025-08-11 14:02:31 -07:00 • committed by Marge Bot
parent 71b513a1e9
commit 0712c220ab
2 changed files with 33 additions and 14 deletions
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20
src/intel/compiler/brw_nir.c
View file

@ -2118,16 +2118,11 @@ nir_shader_has_local_variables(const nir_shader *nir)
/* Prepare the given shader for codegen
*
* This function is intended to be called right before going into the actual
* backend and is highly backend-specific. Also, once this function has been
* called on a shader, it will no longer be in SSA form so most optimizations
* will not work.
* backend and is highly backend-specific.
*/
void
brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
unsigned dispatch_width,
debug_archiver *archiver,
bool debug_enabled,
enum brw_robustness_flags robust_flags)
brw_postprocess_nir_opts(nir_shader *nir, const struct brw_compiler *compiler,
enum brw_robustness_flags robust_flags)
{
const struct intel_device_info *devinfo = compiler->devinfo;
@ -2344,6 +2339,15 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
OPT(nir_lower_subgroups, &subgroups_options);
}
}
void
brw_postprocess_nir_out_of_ssa(nir_shader *nir,
unsigned dispatch_width,
debug_archiver *archiver,
bool debug_enabled)
{
UNUSED bool progress; /* Written by OPT */
/* Run fsign lowering again after the last time brw_nir_optimize is called.
* As is the case with conversion lowering (below), brw_nir_optimize can

27
src/intel/compiler/brw_nir.h
View file

@ -232,12 +232,27 @@ bool brw_nir_lower_mem_access_bit_sizes(nir_shader *shader,
bool brw_nir_lower_simd(nir_shader *nir, unsigned dispatch_width);
void brw_postprocess_nir(nir_shader *nir,
const struct brw_compiler *compiler,
unsigned dispatch_width,
debug_archiver *archiver,
bool debug_enabled,
enum brw_robustness_flags robust_flags);
void brw_postprocess_nir_opts(nir_shader *nir,
const struct brw_compiler *compiler,
enum brw_robustness_flags robust_flags);
void brw_postprocess_nir_out_of_ssa(nir_shader *nir,
unsigned dispatch_width,
debug_archiver *archiver,
bool debug_enabled);
static inline void
brw_postprocess_nir(nir_shader *nir,
const struct brw_compiler *compiler,
unsigned dispatch_width,
debug_archiver *archiver,
bool debug_enabled,
enum brw_robustness_flags robust_flags)
{
brw_postprocess_nir_opts(nir, compiler, robust_flags);
brw_postprocess_nir_out_of_ssa(nir, dispatch_width, archiver,
debug_enabled);
}
bool brw_nir_apply_attribute_workarounds(nir_shader *nir,
const uint8_t *attrib_wa_flags);