From 06f02d2cd1cbcc2967c3e0b40635f9ce89cb5993 Mon Sep 17 00:00:00 2001 From: Sagar Ghuge Date: Fri, 22 Aug 2025 22:14:38 -0700 Subject: [PATCH] anv: Add missing L3 flushes We are reading out some of the parameters from IR data structure those have been written previously, on some platforms L3 is not coherent, so explicitly add those flushes. Cc: mesa-stable Signed-off-by: Sagar Ghuge Reviewed-by: Lionel Landwerlin Part-of: (cherry picked from commit 2cd564c1def281631bf6d12045a65a7b9f80ddd0) --- .pick_status.json | 2 +- .../vulkan/genX_acceleration_structure.c | 32 +++++++++++++------ 2 files changed, 23 insertions(+), 11 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index b0f0c1ebab3..eb2f3525388 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -1114,7 +1114,7 @@ "description": "anv: Add missing L3 flushes", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null, "notes": null diff --git a/src/intel/vulkan/genX_acceleration_structure.c b/src/intel/vulkan/genX_acceleration_structure.c index 4c3a68fcef5..ffee6108547 100644 --- a/src/intel/vulkan/genX_acceleration_structure.c +++ b/src/intel/vulkan/genX_acceleration_structure.c @@ -429,6 +429,15 @@ anv_encode_as(VkCommandBuffer commandBuffer, anv_CmdPushConstants2KHR(commandBuffer, &push_info); + /* L1/L2 caches flushes should have been dealt with by pipeline barriers. + * Unfortunately some platforms require L3 flush because CS (reading the + * ir_internal_node_count paramters from vk_ir_header) is not L3 coherent. + */ + if (!ANV_DEVINFO_HAS_COHERENT_L3_CS(cmd_buffer->device->info)) { + anv_add_pending_pipe_bits(cmd_buffer, ANV_PIPE_DATA_CACHE_FLUSH_BIT, + "ir internal node count for dispatch"); + } + struct anv_address indirect_addr = anv_address_from_u64(intermediate_header_addr + offsetof(struct vk_ir_header, ir_internal_node_count)); @@ -485,9 +494,6 @@ anv_init_header(VkCommandBuffer commandBuffer, VkDeviceAddress header_addr = vk_acceleration_structure_get_va(dst); - UNUSED size_t base = offsetof(struct anv_accel_struct_header, - copy_dispatch_size); - uint32_t instance_count = geometry_type == VK_GEOMETRY_TYPE_INSTANCES_KHR ? leaf_count : 0; @@ -497,13 +503,6 @@ anv_init_header(VkCommandBuffer commandBuffer, */ vk_barrier_compute_w_to_compute_r(commandBuffer); - /* VK_BUILD_ACCELERATION_STRUCTURE_ALLOW_COMPACTION_BIT_KHR is set, so we - * want to populate header.compacted_size with the compacted size, which - * needs to be calculated by using ir_header.dst_node_offset, which we'll - * access in the header.comp. - */ - base = offsetof(struct anv_accel_struct_header, instance_count); - VkPipeline pipeline; VkPipelineLayout layout; get_pipeline_spv(device, "header", header_spv, sizeof(header_spv), @@ -530,6 +529,19 @@ anv_init_header(VkCommandBuffer commandBuffer, } else { vk_barrier_compute_w_to_host_r(commandBuffer); + /* L1/L2 caches flushes should have been dealt with by pipeline barriers. + * Unfortunately some platforms require L3 flush because CS (reading the + * dispatch size paramters) is not L3 coherent. + */ + if (!ANV_DEVINFO_HAS_COHERENT_L3_CS(cmd_buffer->device->info)) { + anv_add_pending_pipe_bits(cmd_buffer, ANV_PIPE_DATA_CACHE_FLUSH_BIT, + "copy dispatch size for dispatch"); + genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer); + } + + size_t base = offsetof(struct anv_accel_struct_header, + copy_dispatch_size); + struct anv_accel_struct_header header = {}; header.instance_count = instance_count;