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intel/brw/xe2+: Use active-thread-only barriers available since Xe2+.

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These allow avoiding dead-locks in non-compliant applications that
execute barriers under non-uniform control flow.  They're not expected
to have any major disadvantage so let's enable them unconditionally.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29562>
This commit is contained in:
Francisco Jerez 2023-01-04 12:56:47 -08:00
parent 8e61d32db8
commit 06e4e088a3
1 changed files with 10 additions and 2 deletions
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12
src/intel/compiler/brw_fs_nir.cpp
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@ -2682,14 +2682,22 @@ static void
setup_barrier_message_payload_gfx125(const fs_builder &bld,
const fs_reg &msg_payload)
{
assert(bld.shader->devinfo->verx10 >= 125);
const fs_builder ubld = bld.exec_all().group(1, 0);
const struct intel_device_info *devinfo = bld.shader->devinfo;
assert(devinfo->verx10 >= 125);
/* From BSpec: 54006, mov r0.2[31:24] into m0.2[31:24] and m0.2[23:16] */
fs_reg m0_10ub = horiz_offset(retype(msg_payload, BRW_TYPE_UB), 10);
fs_reg r0_11ub =
stride(suboffset(retype(brw_vec1_grf(0, 0), BRW_TYPE_UB), 11),
0, 1, 0);
bld.exec_all().group(2, 0).MOV(m0_10ub, r0_11ub);
ubld.group(2, 0).MOV(m0_10ub, r0_11ub);
if (devinfo->ver >= 20) {
/* Use an active threads barrier. */
const fs_reg m0_2ud = component(retype(msg_payload, BRW_TYPE_UD), 2);
ubld.OR(m0_2ud, m0_2ud, brw_imm_ud(1u << 8));
}
}
static void