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i915: Tell the kernel when we actually need fence registers on our BOs.
This improves tiled texture performance of OA on my 945 from 25.3fps to 29.0fps, whereas untiled is 28.2fps, by avoiding stalls for fence register changes.
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parent
179d2c0e0b
commit
06d1472ffa
4 changed files with 49 additions and 12 deletions
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@ -226,6 +226,31 @@ intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
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return GL_TRUE;
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}
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GLboolean
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intel_batchbuffer_emit_reloc_fenced(struct intel_batchbuffer *batch,
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drm_intel_bo *buffer,
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uint32_t read_domains, uint32_t write_domain,
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uint32_t delta)
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{
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int ret;
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if (batch->ptr - batch->map > batch->buf->size)
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printf ("bad relocation ptr %p map %p offset %d size %lu\n",
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batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size);
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ret = drm_intel_bo_emit_reloc_fence(batch->buf, batch->ptr - batch->map,
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buffer, delta,
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read_domains, write_domain);
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/*
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* Using the old buffer offset, write in what the right data would
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* be, in case the buffer doesn't move and we can short-circuit the
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* relocation processing in the kernel
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*/
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intel_batchbuffer_emit_dword (batch, buffer->offset + delta);
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return GL_TRUE;
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}
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void
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intel_batchbuffer_data(struct intel_batchbuffer *batch,
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const void *data, GLuint bytes)
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@ -64,6 +64,11 @@ GLboolean intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch,
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uint32_t read_domains,
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uint32_t write_domain,
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uint32_t offset);
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GLboolean intel_batchbuffer_emit_reloc_fenced(struct intel_batchbuffer *batch,
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drm_intel_bo *buffer,
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uint32_t read_domains,
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uint32_t write_domain,
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uint32_t offset);
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void intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch);
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/* Inline functions - might actually be better off with these
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@ -127,6 +132,11 @@ static INLINE uint32_t float_as_int(float f)
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intel_batchbuffer_emit_reloc(intel->batch, buf, \
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read_domains, write_domain, delta); \
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} while (0)
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#define OUT_RELOC_FENCED(buf, read_domains, write_domain, delta) do { \
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assert((unsigned) (delta) < buf->size); \
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intel_batchbuffer_emit_reloc_fenced(intel->batch, buf, \
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read_domains, write_domain, delta); \
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} while (0)
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#define ADVANCE_BATCH() do { \
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unsigned int _n = intel->batch->ptr - intel->batch->emit.start_ptr; \
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@ -188,14 +188,14 @@ intelEmitCopyBlit(struct intel_context *intel,
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OUT_BATCH(BR13 | (uint16_t)dst_pitch);
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OUT_BATCH((dst_y << 16) | dst_x);
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OUT_BATCH((dst_y2 << 16) | dst_x2);
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OUT_RELOC(dst_buffer,
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
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dst_offset);
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OUT_RELOC_FENCED(dst_buffer,
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
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dst_offset);
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OUT_BATCH((src_y << 16) | src_x);
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OUT_BATCH((uint16_t)src_pitch);
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OUT_RELOC(src_buffer,
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I915_GEM_DOMAIN_RENDER, 0,
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src_offset);
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OUT_RELOC_FENCED(src_buffer,
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I915_GEM_DOMAIN_RENDER, 0,
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src_offset);
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ADVANCE_BATCH();
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intel_batchbuffer_emit_mi_flush(intel->batch);
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@ -365,9 +365,9 @@ intelClearWithBlit(GLcontext *ctx, GLbitfield mask)
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OUT_BATCH(BR13);
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OUT_BATCH((y1 << 16) | x1);
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OUT_BATCH((y2 << 16) | x2);
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OUT_RELOC(write_buffer,
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
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0);
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OUT_RELOC_FENCED(write_buffer,
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
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0);
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OUT_BATCH(clear_val);
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ADVANCE_BATCH();
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@ -448,9 +448,9 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
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OUT_BATCH(br13);
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OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
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OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
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OUT_RELOC(dst_buffer,
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
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dst_offset);
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OUT_RELOC_FENCED(dst_buffer,
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
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dst_offset);
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OUT_BATCH(0); /* bg */
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OUT_BATCH(fg_color); /* fg */
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OUT_BATCH(0); /* pattern base addr */
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@ -426,6 +426,8 @@ intel_init_bufmgr(struct intel_screen *intelScreen)
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else
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intelScreen->kernel_exec_fencing = GL_FALSE;
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drm_intel_bufmgr_gem_enable_fenced_relocs(intelScreen->bufmgr);
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intelScreen->named_regions = _mesa_NewHashTable();
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return GL_TRUE;
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