diff --git a/src/intel/compiler/brw_eu_defines.h b/src/intel/compiler/brw_eu_defines.h index 64af9cfa045..36e31021125 100644 --- a/src/intel/compiler/brw_eu_defines.h +++ b/src/intel/compiler/brw_eu_defines.h @@ -280,31 +280,10 @@ enum ENUM_PACKED opcode { SHADER_OPCODE_UNDEF, /** - * Texture sampling opcodes. - * - * LOGICAL opcodes are eventually translated to SHADER_OPCODE_SEND but - * take parameters as individual sources. See enum tex_logical_srcs. + * A sampler instruction, see brw_tex_inst::sampler_opcode enum + * sampler_opcode. */ - SHADER_OPCODE_TEX_LOGICAL, - SHADER_OPCODE_TXD_LOGICAL, - SHADER_OPCODE_TXF_LOGICAL, - SHADER_OPCODE_TXL_LOGICAL, - SHADER_OPCODE_TXS_LOGICAL, - FS_OPCODE_TXB_LOGICAL, - SHADER_OPCODE_TXF_CMS_W_LOGICAL, - SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL, - SHADER_OPCODE_TXF_MCS_LOGICAL, - SHADER_OPCODE_LOD_LOGICAL, - SHADER_OPCODE_TG4_LOGICAL, - SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL, - SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL, - SHADER_OPCODE_TG4_BIAS_LOGICAL, - SHADER_OPCODE_TG4_OFFSET_LOGICAL, - SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL, - SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL, - SHADER_OPCODE_SAMPLEINFO_LOGICAL, - - SHADER_OPCODE_IMAGE_SIZE_LOGICAL, + SHADER_OPCODE_SAMPLER, /** * Combines multiple sources of size 1 into a larger virtual GRF. @@ -571,6 +550,35 @@ enum ENUM_PACKED opcode { SHADER_OPCODE_LOAD_REG, }; +enum sampler_opcode { + /** + * Texture sampling opcodes. + * + * LOGICAL opcodes are eventually translated to SHADER_OPCODE_SEND but + * take parameters as individual sources. See enum tex_logical_srcs. + */ + SAMPLER_OPCODE_TEX_LOGICAL, + SAMPLER_OPCODE_TXD_LOGICAL, + SAMPLER_OPCODE_TXF_LOGICAL, + SAMPLER_OPCODE_TXL_LOGICAL, + SAMPLER_OPCODE_TXS_LOGICAL, + SAMPLER_OPCODE_TXB_LOGICAL, + SAMPLER_OPCODE_TXF_CMS_W_LOGICAL, + SAMPLER_OPCODE_TXF_CMS_W_GFX12_LOGICAL, + SAMPLER_OPCODE_TXF_MCS_LOGICAL, + SAMPLER_OPCODE_LOD_LOGICAL, + SAMPLER_OPCODE_TG4_LOGICAL, + SAMPLER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL, + SAMPLER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL, + SAMPLER_OPCODE_TG4_BIAS_LOGICAL, + SAMPLER_OPCODE_TG4_OFFSET_LOGICAL, + SAMPLER_OPCODE_TG4_OFFSET_LOD_LOGICAL, + SAMPLER_OPCODE_TG4_OFFSET_BIAS_LOGICAL, + SAMPLER_OPCODE_SAMPLEINFO_LOGICAL, + + SAMPLER_OPCODE_IMAGE_SIZE_LOGICAL, +}; + enum send_srcs { /** The 32-bit message descriptor (can be a register) */ SEND_SRC_DESC, diff --git a/src/intel/compiler/brw_from_nir.cpp b/src/intel/compiler/brw_from_nir.cpp index 8fe989ae760..f1660ac323c 100644 --- a/src/intel/compiler/brw_from_nir.cpp +++ b/src/intel/compiler/brw_from_nir.cpp @@ -5919,8 +5919,9 @@ brw_from_nir_emit_intrinsic(nir_to_brw_state &ntb, const brw_builder ubld = bld.scalar_group(); brw_reg tmp = ubld.vgrf(BRW_TYPE_UD, 4); - brw_tex_inst *inst = ubld.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL, + brw_tex_inst *inst = ubld.emit(SHADER_OPCODE_SAMPLER, tmp, srcs, ARRAY_SIZE(srcs))->as_tex(); + inst->sampler_opcode = SAMPLER_OPCODE_IMAGE_SIZE_LOGICAL; inst->size_written = 4 * REG_SIZE * reg_unit(devinfo); for (unsigned c = 0; c < instr->def.num_components; ++c) { @@ -7511,22 +7512,22 @@ brw_from_nir_emit_texture(nir_to_brw_state &ntb, assert(srcs[TEX_LOGICAL_SRC_MCS].file != BAD_FILE || instr->op != nir_texop_txf_ms); - enum opcode opcode; + enum sampler_opcode opcode; switch (instr->op) { case nir_texop_tex: - opcode = SHADER_OPCODE_TEX_LOGICAL; + opcode = SAMPLER_OPCODE_TEX_LOGICAL; break; case nir_texop_txb: - opcode = FS_OPCODE_TXB_LOGICAL; + opcode = SAMPLER_OPCODE_TXB_LOGICAL; break; case nir_texop_txl: - opcode = SHADER_OPCODE_TXL_LOGICAL; + opcode = SAMPLER_OPCODE_TXL_LOGICAL; break; case nir_texop_txd: - opcode = SHADER_OPCODE_TXD_LOGICAL; + opcode = SAMPLER_OPCODE_TXD_LOGICAL; break; case nir_texop_txf: - opcode = SHADER_OPCODE_TXF_LOGICAL; + opcode = SAMPLER_OPCODE_TXF_LOGICAL; break; case nir_texop_txf_ms: /* On Gfx12HP there is only CMS_W available. From the Bspec: Shared @@ -7535,25 +7536,25 @@ brw_from_nir_emit_texture(nir_to_brw_state &ntb, * ld2dms REMOVEDBY(GEN:HAS:1406788836) */ if (devinfo->verx10 >= 125) - opcode = SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL; + opcode = SAMPLER_OPCODE_TXF_CMS_W_GFX12_LOGICAL; else - opcode = SHADER_OPCODE_TXF_CMS_W_LOGICAL; + opcode = SAMPLER_OPCODE_TXF_CMS_W_LOGICAL; break; case nir_texop_txf_ms_mcs_intel: - opcode = SHADER_OPCODE_TXF_MCS_LOGICAL; + opcode = SAMPLER_OPCODE_TXF_MCS_LOGICAL; break; case nir_texop_query_levels: case nir_texop_txs: - opcode = SHADER_OPCODE_TXS_LOGICAL; + opcode = SAMPLER_OPCODE_TXS_LOGICAL; break; case nir_texop_lod: - opcode = SHADER_OPCODE_LOD_LOGICAL; + opcode = SAMPLER_OPCODE_LOD_LOGICAL; break; case nir_texop_tg4: { if (srcs[TEX_LOGICAL_SRC_TG4_OFFSET].file != BAD_FILE) { - opcode = SHADER_OPCODE_TG4_OFFSET_LOGICAL; + opcode = SAMPLER_OPCODE_TG4_OFFSET_LOGICAL; } else { - opcode = SHADER_OPCODE_TG4_LOGICAL; + opcode = SAMPLER_OPCODE_TG4_LOGICAL; if (devinfo->ver >= 20) { /* If SPV_AMD_texture_gather_bias_lod extension is enabled, all * texture gather functions (ie. the ones which do not take the @@ -7562,26 +7563,26 @@ brw_from_nir_emit_texture(nir_to_brw_state &ntb, * stages, base level is used instead. */ if (instr->is_gather_implicit_lod) - opcode = SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL; + opcode = SAMPLER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL; if (got_bias) - opcode = SHADER_OPCODE_TG4_BIAS_LOGICAL; + opcode = SAMPLER_OPCODE_TG4_BIAS_LOGICAL; if (got_lod) - opcode = SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL; + opcode = SAMPLER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL; if (pack_lod_bias_and_offset) { if (got_lod) - opcode = SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL; + opcode = SAMPLER_OPCODE_TG4_OFFSET_LOD_LOGICAL; if (got_bias) - opcode = SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL; + opcode = SAMPLER_OPCODE_TG4_OFFSET_BIAS_LOGICAL; } } } break; } case nir_texop_texture_samples: - opcode = SHADER_OPCODE_SAMPLEINFO_LOGICAL; + opcode = SAMPLER_OPCODE_SAMPLEINFO_LOGICAL; break; default: UNREACHABLE("unknown texture opcode"); @@ -7621,7 +7622,8 @@ brw_from_nir_emit_texture(nir_to_brw_state &ntb, brw_allocate_vgrf_units(*bld.shader, total_regs * reg_unit(devinfo)), dst_type); - brw_tex_inst *tex = bld.emit(opcode, dst, srcs, ARRAY_SIZE(srcs))->as_tex(); + brw_tex_inst *tex = bld.emit(SHADER_OPCODE_SAMPLER, dst, srcs, ARRAY_SIZE(srcs))->as_tex(); + tex->sampler_opcode = opcode; tex->offset = header_bits; tex->size_written = total_regs * grf_size; tex->residency = instr->is_sparse; diff --git a/src/intel/compiler/brw_inst.cpp b/src/intel/compiler/brw_inst.cpp index 9f2771322bc..3789f28cca0 100644 --- a/src/intel/compiler/brw_inst.cpp +++ b/src/intel/compiler/brw_inst.cpp @@ -200,25 +200,7 @@ brw_inst_kind_for_opcode(enum opcode opcode) case SHADER_OPCODE_INTERLOCK: return BRW_KIND_SEND; - case SHADER_OPCODE_TEX_LOGICAL: - case SHADER_OPCODE_TXD_LOGICAL: - case SHADER_OPCODE_TXF_LOGICAL: - case SHADER_OPCODE_TXL_LOGICAL: - case SHADER_OPCODE_TXS_LOGICAL: - case SHADER_OPCODE_IMAGE_SIZE_LOGICAL: - case FS_OPCODE_TXB_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: - case SHADER_OPCODE_TXF_MCS_LOGICAL: - case SHADER_OPCODE_LOD_LOGICAL: - case SHADER_OPCODE_TG4_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOGICAL: - case SHADER_OPCODE_TG4_BIAS_LOGICAL: - case SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL: - case SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL: - case SHADER_OPCODE_SAMPLEINFO_LOGICAL: + case SHADER_OPCODE_SAMPLER: return BRW_KIND_TEX; case SHADER_OPCODE_MEMORY_LOAD_LOGICAL: @@ -506,41 +488,23 @@ brw_inst::components_read(unsigned i) const else return 1; - case SHADER_OPCODE_TEX_LOGICAL: - case SHADER_OPCODE_TXD_LOGICAL: - case SHADER_OPCODE_TXF_LOGICAL: - case SHADER_OPCODE_TXL_LOGICAL: - case SHADER_OPCODE_TXS_LOGICAL: - case SHADER_OPCODE_IMAGE_SIZE_LOGICAL: - case FS_OPCODE_TXB_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: - case SHADER_OPCODE_TXF_MCS_LOGICAL: - case SHADER_OPCODE_LOD_LOGICAL: - case SHADER_OPCODE_TG4_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOGICAL: - case SHADER_OPCODE_TG4_BIAS_LOGICAL: - case SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL: - case SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL: - case SHADER_OPCODE_SAMPLEINFO_LOGICAL: { + case SHADER_OPCODE_SAMPLER: { const brw_tex_inst *tex = as_tex(); /* Texture coordinates. */ if (i == TEX_LOGICAL_SRC_COORDINATE) return tex->coord_components; /* Texture derivatives. */ else if ((i == TEX_LOGICAL_SRC_LOD || i == TEX_LOGICAL_SRC_LOD2) && - opcode == SHADER_OPCODE_TXD_LOGICAL) + tex->sampler_opcode == SAMPLER_OPCODE_TXD_LOGICAL) return tex->grad_components; /* Texture offset. */ else if (i == TEX_LOGICAL_SRC_TG4_OFFSET) return 2; /* MCS */ else if (i == TEX_LOGICAL_SRC_MCS) { - if (opcode == SHADER_OPCODE_TXF_CMS_W_LOGICAL) + if (tex->sampler_opcode == SAMPLER_OPCODE_TXF_CMS_W_LOGICAL) return 2; - else if (opcode == SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL) + else if (tex->sampler_opcode == SAMPLER_OPCODE_TXF_CMS_W_GFX12_LOGICAL) return 4; else return 1; diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h index fe70f0bec29..46dd00f329f 100644 --- a/src/intel/compiler/brw_inst.h +++ b/src/intel/compiler/brw_inst.h @@ -275,6 +275,7 @@ struct brw_send_inst : brw_inst { }; struct brw_tex_inst : brw_inst { + enum sampler_opcode sampler_opcode; uint32_t offset; uint8_t coord_components; uint8_t grad_components; diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp index e66a102e1bd..f5cb366453a 100644 --- a/src/intel/compiler/brw_lower_logical_sends.cpp +++ b/src/intel/compiler/brw_lower_logical_sends.cpp @@ -606,11 +606,11 @@ is_high_sampler(const struct intel_device_info *devinfo, const brw_reg &sampler) static unsigned sampler_msg_type(const intel_device_info *devinfo, - opcode opcode, bool shadow_compare, + sampler_opcode opcode, bool shadow_compare, bool lod_is_zero, bool has_min_lod) { switch (opcode) { - case SHADER_OPCODE_TEX_LOGICAL: + case SAMPLER_OPCODE_TEX_LOGICAL: if (devinfo->ver >= 20 && has_min_lod) { return shadow_compare ? XE2_SAMPLER_MESSAGE_SAMPLE_COMPARE_MLOD : XE2_SAMPLER_MESSAGE_SAMPLE_MLOD; @@ -618,10 +618,10 @@ sampler_msg_type(const intel_device_info *devinfo, return shadow_compare ? GFX5_SAMPLER_MESSAGE_SAMPLE_COMPARE : GFX5_SAMPLER_MESSAGE_SAMPLE; } - case FS_OPCODE_TXB_LOGICAL: + case SAMPLER_OPCODE_TXB_LOGICAL: return shadow_compare ? GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE : GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS; - case SHADER_OPCODE_TXL_LOGICAL: + case SAMPLER_OPCODE_TXL_LOGICAL: assert(!has_min_lod); if (lod_is_zero) { return shadow_compare ? GFX9_SAMPLER_MESSAGE_SAMPLE_C_LZ : @@ -629,60 +629,60 @@ sampler_msg_type(const intel_device_info *devinfo, } return shadow_compare ? GFX5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE : GFX5_SAMPLER_MESSAGE_SAMPLE_LOD; - case SHADER_OPCODE_TXS_LOGICAL: - case SHADER_OPCODE_IMAGE_SIZE_LOGICAL: + case SAMPLER_OPCODE_TXS_LOGICAL: + case SAMPLER_OPCODE_IMAGE_SIZE_LOGICAL: assert(!has_min_lod); return GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO; - case SHADER_OPCODE_TXD_LOGICAL: + case SAMPLER_OPCODE_TXD_LOGICAL: return shadow_compare ? HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE : GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS; - case SHADER_OPCODE_TXF_LOGICAL: + case SAMPLER_OPCODE_TXF_LOGICAL: assert(!has_min_lod); return lod_is_zero ? GFX9_SAMPLER_MESSAGE_SAMPLE_LD_LZ : GFX5_SAMPLER_MESSAGE_SAMPLE_LD; - case SHADER_OPCODE_TXF_CMS_W_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: + case SAMPLER_OPCODE_TXF_CMS_W_LOGICAL: + case SAMPLER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: assert(!has_min_lod); return GFX9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W; - case SHADER_OPCODE_TXF_MCS_LOGICAL: + case SAMPLER_OPCODE_TXF_MCS_LOGICAL: assert(!has_min_lod); return GFX7_SAMPLER_MESSAGE_SAMPLE_LD_MCS; - case SHADER_OPCODE_LOD_LOGICAL: + case SAMPLER_OPCODE_LOD_LOGICAL: assert(!has_min_lod); return GFX5_SAMPLER_MESSAGE_LOD; - case SHADER_OPCODE_TG4_LOGICAL: + case SAMPLER_OPCODE_TG4_LOGICAL: assert(!has_min_lod); return shadow_compare ? GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C : GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4; break; - case SHADER_OPCODE_TG4_OFFSET_LOGICAL: + case SAMPLER_OPCODE_TG4_OFFSET_LOGICAL: assert(!has_min_lod); return shadow_compare ? GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C : GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO; - case SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL: + case SAMPLER_OPCODE_TG4_OFFSET_LOD_LOGICAL: assert(!has_min_lod); assert(devinfo->ver >= 20); return shadow_compare ? XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_L_C: XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_L; - case SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL: + case SAMPLER_OPCODE_TG4_OFFSET_BIAS_LOGICAL: assert(!has_min_lod); assert(devinfo->ver >= 20); return XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_B; - case SHADER_OPCODE_TG4_BIAS_LOGICAL: + case SAMPLER_OPCODE_TG4_BIAS_LOGICAL: assert(!has_min_lod); assert(devinfo->ver >= 20); return XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_B; - case SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL: + case SAMPLER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL: assert(!has_min_lod); assert(devinfo->ver >= 20); return shadow_compare ? XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_L_C : XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_L; - case SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL: + case SAMPLER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL: assert(!has_min_lod); assert(devinfo->ver >= 20); return shadow_compare ? XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_I_C : XE2_SAMPLER_MESSAGE_SAMPLE_GATHER4_I; - case SHADER_OPCODE_SAMPLEINFO_LOGICAL: + case SAMPLER_OPCODE_SAMPLEINFO_LOGICAL: assert(!has_min_lod); return GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO; default: @@ -733,20 +733,20 @@ emit_load_payload_with_padding(const brw_builder &bld, const brw_reg &dst, } static bool -shader_opcode_needs_header(opcode op, +shader_opcode_needs_header(sampler_opcode op, const struct intel_device_info *devinfo) { switch (op) { - case SHADER_OPCODE_TG4_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL: - case SHADER_OPCODE_TG4_BIAS_LOGICAL: - case SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL: - case SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL: - case SHADER_OPCODE_SAMPLEINFO_LOGICAL: + case SAMPLER_OPCODE_TG4_LOGICAL: + case SAMPLER_OPCODE_TG4_OFFSET_LOGICAL: + case SAMPLER_OPCODE_TG4_OFFSET_BIAS_LOGICAL: + case SAMPLER_OPCODE_TG4_OFFSET_LOD_LOGICAL: + case SAMPLER_OPCODE_TG4_BIAS_LOGICAL: + case SAMPLER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL: + case SAMPLER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL: + case SAMPLER_OPCODE_SAMPLEINFO_LOGICAL: return true; - case SHADER_OPCODE_TXF_LOGICAL: + case SAMPLER_OPCODE_TXF_LOGICAL: /* Xe3 HW does not seem to work unless we force a header. */ return devinfo->ver >= 30; default: @@ -757,13 +757,13 @@ shader_opcode_needs_header(opcode op, } static bool -shader_opcode_uses_sampler(opcode op) +sampler_opcode_uses_sampler_state(sampler_opcode op) { switch (op) { - case SHADER_OPCODE_SAMPLEINFO_LOGICAL: - case SHADER_OPCODE_TXF_LOGICAL: - case SHADER_OPCODE_TXS_LOGICAL: - case SHADER_OPCODE_IMAGE_SIZE_LOGICAL: + case SAMPLER_OPCODE_SAMPLEINFO_LOGICAL: + case SAMPLER_OPCODE_TXF_LOGICAL: + case SAMPLER_OPCODE_TXS_LOGICAL: + case SAMPLER_OPCODE_IMAGE_SIZE_LOGICAL: return false; default: @@ -773,7 +773,7 @@ shader_opcode_uses_sampler(opcode op) static unsigned get_sampler_msg_payload_type_bit_size(const intel_device_info *devinfo, - const brw_inst *inst) + const brw_tex_inst *inst) { assert(inst); const brw_reg *src = inst->src; @@ -797,7 +797,7 @@ get_sampler_msg_payload_type_bit_size(const intel_device_info *devinfo, * which is already in 16-bits unlike the other parameters that need forced * conversion. */ - if (inst->opcode != SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL) { + if (inst->sampler_opcode != SAMPLER_OPCODE_TXF_CMS_W_GFX12_LOGICAL) { for (unsigned i = 0; i < TEX_LOGICAL_NUM_SRCS; i++) { /* surface/sampler don't go in the payload */ if (i == TEX_LOGICAL_SRC_SURFACE || @@ -822,8 +822,8 @@ get_sampler_msg_payload_type_bit_size(const intel_device_info *devinfo, * ld_mcs SIMD8H and SIMD16H Only * ld2dms REMOVEDBY(GEN:HAS:1406788836) */ - if (inst->opcode == SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL || - inst->opcode == SHADER_OPCODE_TXF_MCS_LOGICAL) + if (inst->sampler_opcode == SAMPLER_OPCODE_TXF_CMS_W_GFX12_LOGICAL || + inst->sampler_opcode == SAMPLER_OPCODE_TXF_MCS_LOGICAL) src_type_size = 2; return src_type_size * 8; @@ -864,7 +864,7 @@ lower_sampler_logical_send(const brw_builder &bld, brw_tex_inst *tex) const enum brw_reg_type payload_signed_type = brw_type_with_size(BRW_TYPE_D, payload_type_bit_size); unsigned header_size = 0, length = 0; - opcode op = tex->opcode; + sampler_opcode op = tex->sampler_opcode; brw_reg sources[1 + MAX_SAMPLER_MESSAGE_SIZE]; for (unsigned i = 0; i < ARRAY_SIZE(sources); i++) sources[i] = bld.vgrf(payload_type); @@ -973,7 +973,7 @@ lower_sampler_logical_send(const brw_builder &bld, brw_tex_inst *tex) ubld.SHL(tmp, tmp, brw_imm_ud(4)); ubld1.ADD(component(header, 3), sampler_state_ptr, tmp); } - } else if (devinfo->ver >= 11 && shader_opcode_uses_sampler(op)) { + } else if (devinfo->ver >= 11 && sampler_opcode_uses_sampler_state(op)) { /* Gfx11+ sampler message headers include bits in 4:0 which conflict * with the ones included in g0.3 bits 4:0. Mask them out. */ @@ -1011,19 +1011,19 @@ lower_sampler_logical_send(const brw_builder &bld, brw_tex_inst *tex) /* Set up the LOD info */ switch (op) { - case SHADER_OPCODE_TXL_LOGICAL: + case SAMPLER_OPCODE_TXL_LOGICAL: if (lod_is_zero) break; FALLTHROUGH; - case FS_OPCODE_TXB_LOGICAL: - case SHADER_OPCODE_TG4_BIAS_LOGICAL: - case SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL: + case SAMPLER_OPCODE_TXB_LOGICAL: + case SAMPLER_OPCODE_TG4_BIAS_LOGICAL: + case SAMPLER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL: + case SAMPLER_OPCODE_TG4_OFFSET_LOD_LOGICAL: + case SAMPLER_OPCODE_TG4_OFFSET_BIAS_LOGICAL: bld.MOV(sources[length], lod); length++; break; - case SHADER_OPCODE_TXD_LOGICAL: + case SAMPLER_OPCODE_TXD_LOGICAL: /* TXD should have been lowered in SIMD16 mode (in SIMD32 mode in * Xe2+). */ @@ -1046,16 +1046,16 @@ lower_sampler_logical_send(const brw_builder &bld, brw_tex_inst *tex) coordinate_done = true; break; - case SHADER_OPCODE_TXS_LOGICAL: + case SAMPLER_OPCODE_TXS_LOGICAL: sources[length] = retype(sources[length], payload_unsigned_type); bld.MOV(sources[length++], lod); break; - case SHADER_OPCODE_IMAGE_SIZE_LOGICAL: + case SAMPLER_OPCODE_IMAGE_SIZE_LOGICAL: /* We need an LOD; just use 0 */ sources[length] = retype(sources[length], payload_unsigned_type); bld.MOV(sources[length++], brw_imm_ud(0)); break; - case SHADER_OPCODE_TXF_LOGICAL: + case SAMPLER_OPCODE_TXF_LOGICAL: /* On Gfx9 the parameters are intermixed they are u, v, lod, r. */ sources[length] = retype(sources[length], payload_signed_type); bld.MOV(sources[length++], offset(coordinate, bld, 0)); @@ -1081,8 +1081,8 @@ lower_sampler_logical_send(const brw_builder &bld, brw_tex_inst *tex) coordinate_done = true; break; - case SHADER_OPCODE_TXF_CMS_W_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: + case SAMPLER_OPCODE_TXF_CMS_W_LOGICAL: + case SAMPLER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: sources[length] = retype(sources[length], payload_unsigned_type); bld.MOV(sources[length++], sample_index); @@ -1098,7 +1098,7 @@ lower_sampler_logical_send(const brw_builder &bld, brw_tex_inst *tex) * * ld2dms_w si mcs0 mcs1 mcs2 mcs3 u v r */ - if (op == SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL) { + if (op == SAMPLER_OPCODE_TXF_CMS_W_GFX12_LOGICAL) { sources[length] = retype(sources[length], payload_unsigned_type); bld.MOV(sources[length++], mcs.file == IMM ? mcs : offset(mcs, bld, 2 * i + 0)); @@ -1114,7 +1114,7 @@ lower_sampler_logical_send(const brw_builder &bld, brw_tex_inst *tex) } FALLTHROUGH; - case SHADER_OPCODE_TXF_MCS_LOGICAL: + case SAMPLER_OPCODE_TXF_MCS_LOGICAL: /* There is no offsetting for this message; just copy in the integer * texture coordinates. */ @@ -1125,7 +1125,7 @@ lower_sampler_logical_send(const brw_builder &bld, brw_tex_inst *tex) coordinate_done = true; break; - case SHADER_OPCODE_TG4_OFFSET_LOGICAL: + case SAMPLER_OPCODE_TG4_OFFSET_LOGICAL: /* More crazy intermixing */ for (unsigned i = 0; i < 2; i++) /* u, v */ bld.MOV(sources[length++], offset(coordinate, bld, i)); @@ -1153,7 +1153,7 @@ lower_sampler_logical_send(const brw_builder &bld, brw_tex_inst *tex) if (min_lod.file != BAD_FILE && !min_lod_is_first) { /* Account for all of the missing coordinate sources */ - if (op == FS_OPCODE_TXB_LOGICAL && devinfo->ver >= 20) { + if (op == SAMPLER_OPCODE_TXB_LOGICAL && devinfo->ver >= 20) { /* Bspec 64985: * * For sample_b sampler message format: @@ -1167,7 +1167,7 @@ lower_sampler_logical_send(const brw_builder &bld, brw_tex_inst *tex) * Param BIAS_AI U V R MLOD */ length += 3 - tex->coord_components; - } else if (op == SHADER_OPCODE_TXD_LOGICAL && devinfo->verx10 >= 125) { + } else if (op == SAMPLER_OPCODE_TXD_LOGICAL && devinfo->verx10 >= 125) { /* On DG2 and newer platforms, sample_d can only be used with 1D and * 2D surfaces, so the maximum number of gradient components is 2. * In spite of this limitation, the Bspec lists a mysterious R @@ -1180,7 +1180,7 @@ lower_sampler_logical_send(const brw_builder &bld, brw_tex_inst *tex) length += (2 - tex->grad_components) * 2; } else { length += 4 - tex->coord_components; - if (op == SHADER_OPCODE_TXD_LOGICAL) + if (op == SAMPLER_OPCODE_TXD_LOGICAL) length += (3 - tex->grad_components) * 2; } @@ -1188,7 +1188,7 @@ lower_sampler_logical_send(const brw_builder &bld, brw_tex_inst *tex) /* Wa_14014595444: Populate MLOD as parameter 5 (twice). */ if (intel_needs_workaround(devinfo, 14014595444) && - op == FS_OPCODE_TXB_LOGICAL && shadow_c.file == BAD_FILE) + op == SAMPLER_OPCODE_TXB_LOGICAL && shadow_c.file == BAD_FILE) bld.MOV(sources[length++], min_lod); } @@ -2613,25 +2613,7 @@ brw_lower_logical_sends(brw_shader &s) lower_fb_read_logical_send(ibld, inst, brw_wm_prog_data(s.prog_data)); break; - case SHADER_OPCODE_TEX_LOGICAL: - case SHADER_OPCODE_TXD_LOGICAL: - case SHADER_OPCODE_TXF_LOGICAL: - case SHADER_OPCODE_TXL_LOGICAL: - case SHADER_OPCODE_TXS_LOGICAL: - case SHADER_OPCODE_IMAGE_SIZE_LOGICAL: - case FS_OPCODE_TXB_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: - case SHADER_OPCODE_TXF_MCS_LOGICAL: - case SHADER_OPCODE_LOD_LOGICAL: - case SHADER_OPCODE_TG4_LOGICAL: - case SHADER_OPCODE_TG4_BIAS_LOGICAL: - case SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL: - case SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL: - case SHADER_OPCODE_SAMPLEINFO_LOGICAL: + case SHADER_OPCODE_SAMPLER: lower_sampler_logical_send(ibld, inst->as_tex()); break; diff --git a/src/intel/compiler/brw_lower_simd_width.cpp b/src/intel/compiler/brw_lower_simd_width.cpp index 243f930670e..3a7c8b2bb92 100644 --- a/src/intel/compiler/brw_lower_simd_width.cpp +++ b/src/intel/compiler/brw_lower_simd_width.cpp @@ -162,19 +162,31 @@ static unsigned get_sampler_lowered_simd_width(const struct intel_device_info *devinfo, const brw_tex_inst *tex) { + /* On gfx12 parameters are fixed to 16-bit values and therefore they all + * always fit regardless of the execution size. + */ + if (tex->sampler_opcode == SAMPLER_OPCODE_TXF_CMS_W_GFX12_LOGICAL) + return MIN2(16, tex->exec_size); + + /* TXD is unsupported in SIMD16 mode previous to Xe2. SIMD32 is still + * unsuppported on Xe2. + */ + if (tex->sampler_opcode == SAMPLER_OPCODE_TXD_LOGICAL) + return devinfo->ver < 20 ? 8 : 16; + /* If we have a min_lod parameter on anything other than a simple sample * message, it will push it over 5 arguments and we have to fall back to * SIMD8. */ - if (tex->opcode != SHADER_OPCODE_TEX_LOGICAL && + if (tex->sampler_opcode != SAMPLER_OPCODE_TEX_LOGICAL && tex->components_read(TEX_LOGICAL_SRC_MIN_LOD)) return devinfo->ver < 20 ? 8 : 16; /* On Gfx9+ the LOD argument is for free if we're able to use the LZ * variant of the TXL or TXF message. */ - const bool implicit_lod = (tex->opcode == SHADER_OPCODE_TXL_LOGICAL || - tex->opcode == SHADER_OPCODE_TXF_LOGICAL) && + const bool implicit_lod = (tex->sampler_opcode == SAMPLER_OPCODE_TXL_LOGICAL || + tex->sampler_opcode == SAMPLER_OPCODE_TXF_LOGICAL) && tex->src[TEX_LOGICAL_SRC_LOD].is_zero(); /* Calculate the total number of argument components that need to be passed @@ -186,21 +198,21 @@ get_sampler_lowered_simd_width(const struct intel_device_info *devinfo, (implicit_lod ? 0 : tex->components_read(TEX_LOGICAL_SRC_LOD)) + tex->components_read(TEX_LOGICAL_SRC_LOD2) + tex->components_read(TEX_LOGICAL_SRC_SAMPLE_INDEX) + - (tex->opcode == SHADER_OPCODE_TG4_OFFSET_LOGICAL ? + (tex->sampler_opcode == SAMPLER_OPCODE_TG4_OFFSET_LOGICAL ? tex->components_read(TEX_LOGICAL_SRC_TG4_OFFSET) : 0) + tex->components_read(TEX_LOGICAL_SRC_MCS) + tex->components_read(TEX_LOGICAL_SRC_MIN_LOD); - if (tex->opcode == FS_OPCODE_TXB_LOGICAL && devinfo->ver >= 20) { + if (tex->sampler_opcode == SAMPLER_OPCODE_TXB_LOGICAL && devinfo->ver >= 20) { num_payload_components += 3 - tex->coord_components; - } else if (tex->opcode == SHADER_OPCODE_TXD_LOGICAL && + } else if (tex->sampler_opcode == SAMPLER_OPCODE_TXD_LOGICAL && devinfo->verx10 >= 125 && devinfo->ver < 20) { num_payload_components += 3 - tex->coord_components + (2 - tex->grad_components) * 2; } else { num_payload_components += 4 - tex->coord_components; - if (tex->opcode == SHADER_OPCODE_TXD_LOGICAL) + if (tex->sampler_opcode == SAMPLER_OPCODE_TXD_LOGICAL) num_payload_components += (3 - tex->grad_components) * 2; } @@ -356,22 +368,7 @@ brw_get_lowered_simd_width(const brw_shader *shader, const brw_inst *inst) case FS_OPCODE_FB_READ_LOGICAL: return MIN2(16, inst->exec_size); - case SHADER_OPCODE_TEX_LOGICAL: - case SHADER_OPCODE_TXF_MCS_LOGICAL: - case SHADER_OPCODE_LOD_LOGICAL: - case SHADER_OPCODE_TG4_LOGICAL: - case SHADER_OPCODE_SAMPLEINFO_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOGICAL: - case SHADER_OPCODE_TG4_BIAS_LOGICAL: - case SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL: - case SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL: - case SHADER_OPCODE_TXL_LOGICAL: - case FS_OPCODE_TXB_LOGICAL: - case SHADER_OPCODE_TXF_LOGICAL: - case SHADER_OPCODE_TXS_LOGICAL: + case SHADER_OPCODE_SAMPLER: return get_sampler_lowered_simd_width(devinfo, inst->as_tex()); case SHADER_OPCODE_MEMORY_LOAD_LOGICAL: @@ -394,18 +391,6 @@ brw_get_lowered_simd_width(const brw_shader *shader, const brw_inst *inst) return MIN2(16, mem->exec_size); } - /* On gfx12 parameters are fixed to 16-bit values and therefore they all - * always fit regardless of the execution size. - */ - case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: - return MIN2(16, inst->exec_size); - - case SHADER_OPCODE_TXD_LOGICAL: - /* TXD is unsupported in SIMD16 mode previous to Xe2. SIMD32 is still - * unsuppported on Xe2. - */ - return devinfo->ver < 20 ? 8 : 16; - case SHADER_OPCODE_URB_READ_LOGICAL: case SHADER_OPCODE_URB_WRITE_LOGICAL: return MIN2(devinfo->ver < 20 ? 8 : 16, inst->exec_size); diff --git a/src/intel/compiler/brw_opt_copy_propagation.cpp b/src/intel/compiler/brw_opt_copy_propagation.cpp index 9edd1146770..eac3936375f 100644 --- a/src/intel/compiler/brw_opt_copy_propagation.cpp +++ b/src/intel/compiler/brw_opt_copy_propagation.cpp @@ -1260,25 +1260,7 @@ try_constant_propagate_value(const intel_device_info *devinfo, case BRW_OPCODE_SHL: case BRW_OPCODE_SHR: case BRW_OPCODE_OR: - case SHADER_OPCODE_TEX_LOGICAL: - case SHADER_OPCODE_TXD_LOGICAL: - case SHADER_OPCODE_TXF_LOGICAL: - case SHADER_OPCODE_TXL_LOGICAL: - case SHADER_OPCODE_TXS_LOGICAL: - case FS_OPCODE_TXB_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: - case SHADER_OPCODE_TXF_MCS_LOGICAL: - case SHADER_OPCODE_LOD_LOGICAL: - case SHADER_OPCODE_TG4_BIAS_LOGICAL: - case SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL: - case SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL: - case SHADER_OPCODE_TG4_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL: - case SHADER_OPCODE_SAMPLEINFO_LOGICAL: - case SHADER_OPCODE_IMAGE_SIZE_LOGICAL: + case SHADER_OPCODE_SAMPLER: case SHADER_OPCODE_MEMORY_LOAD_LOGICAL: case SHADER_OPCODE_MEMORY_STORE_LOGICAL: case SHADER_OPCODE_MEMORY_ATOMIC_LOGICAL: diff --git a/src/intel/compiler/brw_opt_cse.cpp b/src/intel/compiler/brw_opt_cse.cpp index b5fb8c86e70..68342a530e0 100644 --- a/src/intel/compiler/brw_opt_cse.cpp +++ b/src/intel/compiler/brw_opt_cse.cpp @@ -93,25 +93,7 @@ is_expression(const brw_shader *v, const brw_inst *const inst) case SHADER_OPCODE_QUAD_SWIZZLE: case SHADER_OPCODE_CLUSTER_BROADCAST: case SHADER_OPCODE_MOV_INDIRECT: - case SHADER_OPCODE_TEX_LOGICAL: - case SHADER_OPCODE_TXD_LOGICAL: - case SHADER_OPCODE_TXF_LOGICAL: - case SHADER_OPCODE_TXL_LOGICAL: - case SHADER_OPCODE_TXS_LOGICAL: - case FS_OPCODE_TXB_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: - case SHADER_OPCODE_TXF_MCS_LOGICAL: - case SHADER_OPCODE_LOD_LOGICAL: - case SHADER_OPCODE_TG4_LOGICAL: - case SHADER_OPCODE_TG4_BIAS_LOGICAL: - case SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL: - case SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL: - case SHADER_OPCODE_SAMPLEINFO_LOGICAL: - case SHADER_OPCODE_IMAGE_SIZE_LOGICAL: + case SHADER_OPCODE_SAMPLER: case SHADER_OPCODE_GET_BUFFER_SIZE: case FS_OPCODE_PACK: case FS_OPCODE_PACK_HALF_2x16_SPLIT: @@ -256,7 +238,8 @@ send_inst_match(brw_send_inst *a, brw_send_inst *b) static bool tex_inst_match(brw_tex_inst *a, brw_tex_inst *b) { - return a->offset == b->offset && + return a->sampler_opcode == b->sampler_opcode && + a->offset == b->offset && a->coord_components == b->coord_components && a->grad_components == b->grad_components && a->residency == b->residency; @@ -408,7 +391,11 @@ hash_inst(const void *v) tex->grad_components, tex->residency, }; + const uint32_t tex_u32data[] = { + tex->sampler_opcode, + }; hash = HASH(hash, tex_u8data); + hash = HASH(hash, tex_u32data); break; } diff --git a/src/intel/compiler/brw_opt_txf_combiner.cpp b/src/intel/compiler/brw_opt_txf_combiner.cpp index 623474f7188..ab6a30c0e2a 100644 --- a/src/intel/compiler/brw_opt_txf_combiner.cpp +++ b/src/intel/compiler/brw_opt_txf_combiner.cpp @@ -94,10 +94,12 @@ brw_opt_combine_convergent_txf(brw_shader &s) unsigned count = 0; foreach_inst_in_block(brw_inst, inst, block) { - if (inst->opcode != SHADER_OPCODE_TXF_LOGICAL) + brw_tex_inst *tex = inst->as_tex(); + if (tex == NULL) continue; - brw_tex_inst *tex = inst->as_tex(); + if (tex->sampler_opcode != SAMPLER_OPCODE_TXF_LOGICAL) + continue; /* Only handle buffers or single miplevel 1D images for now */ if (tex->coord_components > 1) @@ -193,8 +195,9 @@ brw_opt_combine_convergent_txf(brw_shader &s) /* Emit the new divergent TXF */ brw_reg div = ubld.vgrf(BRW_TYPE_UD, new_dest_comps); brw_tex_inst *div_txf = - ubld.emit(SHADER_OPCODE_TXF_LOGICAL, div, srcs, + ubld.emit(SHADER_OPCODE_SAMPLER, div, srcs, TEX_LOGICAL_NUM_SRCS)->as_tex(); + div_txf->sampler_opcode = SAMPLER_OPCODE_TXF_LOGICAL; div_txf->coord_components = 1; div_txf->grad_components = 0; div_txf->residency = false; diff --git a/src/intel/compiler/brw_print.cpp b/src/intel/compiler/brw_print.cpp index 688b993f5bf..1367813078c 100644 --- a/src/intel/compiler/brw_print.cpp +++ b/src/intel/compiler/brw_print.cpp @@ -75,9 +75,36 @@ brw_print_instructions(const brw_shader &s, FILE *file) } static const char * -brw_instruction_name(const struct brw_isa_info *isa, enum opcode op) +brw_sampler_opcode_name(sampler_opcode opcode) { + switch (opcode) { + case SAMPLER_OPCODE_TEX_LOGICAL: return "tex_logical"; + case SAMPLER_OPCODE_TXD_LOGICAL: return "txd_logical"; + case SAMPLER_OPCODE_TXF_LOGICAL: return "txf_logical"; + case SAMPLER_OPCODE_TXL_LOGICAL: return "txl_logical"; + case SAMPLER_OPCODE_TXS_LOGICAL: return "txs_logical"; + case SAMPLER_OPCODE_TXB_LOGICAL: return "txb_logical"; + case SAMPLER_OPCODE_TXF_CMS_W_LOGICAL: return "txf_cms_w_logical"; + case SAMPLER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: return "txf_cms_w_gfx12_logical"; + case SAMPLER_OPCODE_TXF_MCS_LOGICAL: return "txf_mcs_logical"; + case SAMPLER_OPCODE_LOD_LOGICAL: return "lod_logical"; + case SAMPLER_OPCODE_TG4_LOGICAL: return "tg4_logical"; + case SAMPLER_OPCODE_TG4_OFFSET_LOGICAL: return "tg4_offset_logical"; + case SAMPLER_OPCODE_TG4_OFFSET_LOD_LOGICAL: return "tg4_offset_lod_logical"; + case SAMPLER_OPCODE_TG4_OFFSET_BIAS_LOGICAL: return "tg4_offset_bias_logical"; + case SAMPLER_OPCODE_TG4_BIAS_LOGICAL: return "tg4_b_logical"; + case SAMPLER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL: return "tg4_l_logical"; + case SAMPLER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL: return "tg4_i_logical"; + case SAMPLER_OPCODE_SAMPLEINFO_LOGICAL: return "sampleinfo_logical"; + case SAMPLER_OPCODE_IMAGE_SIZE_LOGICAL: return "image_size_logical"; + default: UNREACHABLE("invalid sampler opcode"); + } +} + +static const char * +brw_instruction_name(const struct brw_isa_info *isa, const brw_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; + enum opcode op = inst->opcode; switch (op) { case 0 ... NUM_BRW_OPCODES - 1: @@ -130,45 +157,8 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op) case SHADER_OPCODE_UNDEF: return "undef"; - case SHADER_OPCODE_TEX_LOGICAL: - return "tex_logical"; - case SHADER_OPCODE_TXD_LOGICAL: - return "txd_logical"; - case SHADER_OPCODE_TXF_LOGICAL: - return "txf_logical"; - case SHADER_OPCODE_TXL_LOGICAL: - return "txl_logical"; - case SHADER_OPCODE_TXS_LOGICAL: - return "txs_logical"; - case FS_OPCODE_TXB_LOGICAL: - return "txb_logical"; - case SHADER_OPCODE_TXF_CMS_W_LOGICAL: - return "txf_cms_w_logical"; - case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: - return "txf_cms_w_gfx12_logical"; - case SHADER_OPCODE_TXF_MCS_LOGICAL: - return "txf_mcs_logical"; - case SHADER_OPCODE_LOD_LOGICAL: - return "lod_logical"; - case SHADER_OPCODE_TG4_LOGICAL: - return "tg4_logical"; - case SHADER_OPCODE_TG4_OFFSET_LOGICAL: - return "tg4_offset_logical"; - case SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL: - return "tg4_offset_lod_logical"; - case SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL: - return "tg4_offset_bias_logical"; - case SHADER_OPCODE_TG4_BIAS_LOGICAL: - return "tg4_b_logical"; - case SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL: - return "tg4_l_logical"; - case SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL: - return "tg4_i_logical"; - case SHADER_OPCODE_SAMPLEINFO_LOGICAL: - return "sampleinfo_logical"; - - case SHADER_OPCODE_IMAGE_SIZE_LOGICAL: - return "image_size_logical"; + case SHADER_OPCODE_SAMPLER: + return brw_sampler_opcode_name(inst->as_tex()->sampler_opcode); case SHADER_OPCODE_MEMORY_FENCE: return "memory_fence"; @@ -355,7 +345,7 @@ brw_print_instruction(const brw_shader &s, const brw_inst *inst, FILE *file, con inst->flag_subreg % 2); } - fprintf(file, "%s", brw_instruction_name(&s.compiler->isa, inst->opcode)); + fprintf(file, "%s", brw_instruction_name(&s.compiler->isa, inst)); if (inst->saturate) fprintf(file, ".sat"); if (inst->conditional_mod) { diff --git a/src/intel/compiler/brw_validate.cpp b/src/intel/compiler/brw_validate.cpp index 8add43563b1..ee53339a094 100644 --- a/src/intel/compiler/brw_validate.cpp +++ b/src/intel/compiler/brw_validate.cpp @@ -200,25 +200,7 @@ brw_validate_instruction_phase(const brw_shader &s, brw_inst *inst) switch (inst->opcode) { case FS_OPCODE_FB_WRITE_LOGICAL: case FS_OPCODE_FB_READ_LOGICAL: - case SHADER_OPCODE_TEX_LOGICAL: - case SHADER_OPCODE_TXD_LOGICAL: - case SHADER_OPCODE_TXF_LOGICAL: - case SHADER_OPCODE_TXL_LOGICAL: - case SHADER_OPCODE_TXS_LOGICAL: - case SHADER_OPCODE_IMAGE_SIZE_LOGICAL: - case FS_OPCODE_TXB_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_LOGICAL: - case SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL: - case SHADER_OPCODE_TXF_MCS_LOGICAL: - case SHADER_OPCODE_LOD_LOGICAL: - case SHADER_OPCODE_TG4_LOGICAL: - case SHADER_OPCODE_TG4_BIAS_LOGICAL: - case SHADER_OPCODE_TG4_EXPLICIT_LOD_LOGICAL: - case SHADER_OPCODE_TG4_IMPLICIT_LOD_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_LOD_LOGICAL: - case SHADER_OPCODE_TG4_OFFSET_BIAS_LOGICAL: - case SHADER_OPCODE_SAMPLEINFO_LOGICAL: + case SHADER_OPCODE_SAMPLER: case SHADER_OPCODE_GET_BUFFER_SIZE: case SHADER_OPCODE_MEMORY_LOAD_LOGICAL: case SHADER_OPCODE_MEMORY_STORE_LOGICAL: diff --git a/src/intel/compiler/test_opt_cmod_propagation.cpp b/src/intel/compiler/test_opt_cmod_propagation.cpp index db8def0a5d6..84f28f56b96 100644 --- a/src/intel/compiler/test_opt_cmod_propagation.cpp +++ b/src/intel/compiler/test_opt_cmod_propagation.cpp @@ -216,7 +216,7 @@ TEST_F(cmod_propagation_test, intervening_dest_write) bld.ADD(offset(dest, bld, 2), src0, src1); brw_tex_inst *tex = - bld.emit(SHADER_OPCODE_TEX_LOGICAL, dest, tex_srcs, TEX_LOGICAL_NUM_SRCS)->as_tex(); + bld.emit(SHADER_OPCODE_SAMPLER, dest, tex_srcs, TEX_LOGICAL_NUM_SRCS)->as_tex(); tex->size_written = 4 * REG_SIZE; tex->coord_components = 2; diff --git a/src/intel/compiler/test_opt_saturate_propagation.cpp b/src/intel/compiler/test_opt_saturate_propagation.cpp index 7267cdaaebc..241cfeceb33 100644 --- a/src/intel/compiler/test_opt_saturate_propagation.cpp +++ b/src/intel/compiler/test_opt_saturate_propagation.cpp @@ -281,7 +281,7 @@ TEST_F(saturate_propagation_test, intervening_dest_write) bld.ADD(offset(dst0, bld, 2), src0, src1); brw_tex_inst *tex = - bld.emit(SHADER_OPCODE_TEX_LOGICAL, dst0, tex_srcs, TEX_LOGICAL_NUM_SRCS)->as_tex(); + bld.emit(SHADER_OPCODE_SAMPLER, dst0, tex_srcs, TEX_LOGICAL_NUM_SRCS)->as_tex(); tex->size_written = 8 * REG_SIZE; tex->coord_components = 2;