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freedreno: Move RB_CCU_DBG_ECO_CNTL to raw_magic_regs

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This only needs to be programmed by UMD for a7xx.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38515>
This commit is contained in:
Rob Clark 2025-11-18 14:37:51 -08:00 • committed by Marge Bot
parent 231ff1c14d
commit 062e90f19b
5 changed files with 6 additions and 18 deletions
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2
src/freedreno/common/freedreno_dev_info.h
View file

@ -230,8 +230,6 @@ struct fd_dev_info {
uint32_t RB_DBG_ECO_CNTL;
uint32_t RB_DBG_ECO_CNTL_blit;
uint32_t RB_RBP_CNTL;
uint32_t RB_CCU_DBG_ECO_CNTL;
} magic;
struct {

15
src/freedreno/common/freedreno_devices.py
View file

@ -1023,8 +1023,6 @@ a730_magic_regs = dict(
RB_DBG_ECO_CNTL = 0x00000000,
RB_DBG_ECO_CNTL_blit = 0x00000000, # is it even needed?
RB_RBP_CNTL = 0x0,
RB_CCU_DBG_ECO_CNTL = 0x02080000,
)
a730_raw_magic_regs = [
@ -1066,6 +1064,7 @@ a730_raw_magic_regs = [
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x02080000],
[A6XXRegs.REG_A6XX_VPC_DBG_ECO_CNTL, 0x02000000],
[A6XXRegs.REG_A6XX_UCHE_UNKNOWN_0E12, 0x3200000],
]
@ -1074,8 +1073,6 @@ a740_magic_regs = dict(
RB_DBG_ECO_CNTL = 0x00000000,
RB_DBG_ECO_CNTL_blit = 0x00000000, # is it even needed?
RB_RBP_CNTL = 0x0,
RB_CCU_DBG_ECO_CNTL = 0x02080000,
)
a740_raw_magic_regs = [
@ -1120,6 +1117,7 @@ a740_raw_magic_regs = [
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8C34, 0x00000000],
[A6XXRegs.REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x02080000],
[A6XXRegs.REG_A6XX_VPC_DBG_ECO_CNTL, 0x02000000],
[A6XXRegs.REG_A6XX_UCHE_UNKNOWN_0E12, 0],
]
@ -1178,8 +1176,6 @@ add_gpus([
RB_DBG_ECO_CNTL = 0x00000001,
RB_DBG_ECO_CNTL_blit = 0x00000001, # is it even needed?
RB_RBP_CNTL = 0x0,
RB_CCU_DBG_ECO_CNTL = 0x02080000,
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00000000],
@ -1221,6 +1217,7 @@ add_gpus([
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8C34, 0x00000000],
[A6XXRegs.REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x02080000],
[A6XXRegs.REG_A6XX_VPC_DBG_ECO_CNTL, 0x02000000],
[A6XXRegs.REG_A6XX_UCHE_UNKNOWN_0E12, 0],
],
@ -1302,6 +1299,7 @@ add_gpus([
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8E79, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x02080000],
[A6XXRegs.REG_A6XX_VPC_DBG_ECO_CNTL, 0x02000000],
[A6XXRegs.REG_A6XX_UCHE_UNKNOWN_0E12, 0],
],
@ -1324,8 +1322,6 @@ add_gpus([
RB_DBG_ECO_CNTL = 0x00000001,
RB_DBG_ECO_CNTL_blit = 0x00000000, # is it even needed?
RB_RBP_CNTL = 0x0,
RB_CCU_DBG_ECO_CNTL = 0x02080000,
),
raw_magic_regs = a740_raw_magic_regs,
))
@ -1348,8 +1344,6 @@ add_gpus([
RB_DBG_ECO_CNTL = 0x00000001,
RB_DBG_ECO_CNTL_blit = 0x00000001,
RB_RBP_CNTL = 0x0,
RB_CCU_DBG_ECO_CNTL = 0x02082000,
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00000000],
@ -1386,6 +1380,7 @@ add_gpus([
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8899, 0x00000000],
[A6XXRegs.REG_A7XX_RB_UNKNOWN_8C34, 0x00000000],
[A6XXRegs.REG_A7XX_RB_CCU_DBG_ECO_CNTL, 0x02082000],
[A6XXRegs.REG_A7XX_VPC_UNKNOWN_930A, 0],
[A6XXRegs.REG_A7XX_VPC_FLATSHADE_MODE_CNTL, 1],

2
src/freedreno/vulkan/tu_clear_blit.cc
View file

@ -1609,8 +1609,6 @@ r3d_setup(struct tu_cmd_buffer *cmd,
.rt6_sysmem = true,
.rt7_sysmem = true,
));
tu_cs_emit_regs(cs,
A7XX_RB_CCU_DBG_ECO_CNTL(cmd->device->physical_device->info->a6xx.magic.RB_CCU_DBG_ECO_CNTL));
}
}

2
src/freedreno/vulkan/tu_cmd_buffer.cc
View file

@ -2982,8 +2982,6 @@ tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
.rt6_sysmem = true,
.rt7_sysmem = true,
));
tu_cs_emit_regs(cs,
A7XX_RB_CCU_DBG_ECO_CNTL(cmd->device->physical_device->info->a6xx.magic.RB_CCU_DBG_ECO_CNTL));
tu_cs_emit_regs(cs, GRAS_MODE_CNTL(A7XX, 0x2));
tu_cs_emit_regs(cs, A7XX_RB_UNKNOWN_8E09(0x4));

3
src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
View file

@ -2019,7 +2019,7 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt
.add(GRAS_MODE_CNTL(CHIP, 0x2));
}
with_crb (cs, 11) {
with_crb (cs, 10) {
set_window_offset<CHIP>(crb, 0, 0);
set_bin_size<CHIP>(crb, NULL, {
@ -2040,7 +2040,6 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt
.rt6_sysmem = true,
.rt7_sysmem = true,
));
crb.add(RB_CCU_DBG_ECO_CNTL(CHIP, batch->ctx->screen->info->a6xx.magic.RB_CCU_DBG_ECO_CNTL));
crb.add(GRAS_LRZ_CB_CNTL(CHIP, 0x0));
}