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radeonsi: add another requirement for PARTIAL_ES_WAVE

Browse source 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák 2015-10-19 02:45:56 +02:00
parent 0d2cb35f68
commit 06083046a4
4 changed files with 35 additions and 2 deletions
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29
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -576,6 +576,32 @@ static bool si_initialize_pipe_config(struct si_screen *sscreen)
return true;
}
static bool si_init_gs_info(struct si_screen *sscreen)
{
switch (sscreen->b.family) {
case CHIP_OLAND:
case CHIP_HAINAN:
case CHIP_KAVERI:
case CHIP_KABINI:
case CHIP_MULLINS:
case CHIP_ICELAND:
case CHIP_CARRIZO:
sscreen->gs_table_depth = 16;
return true;
case CHIP_TAHITI:
case CHIP_PITCAIRN:
case CHIP_VERDE:
case CHIP_BONAIRE:
case CHIP_HAWAII:
case CHIP_TONGA:
case CHIP_FIJI:
sscreen->gs_table_depth = 32;
return true;
default:
return false;
}
}
struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
{
struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
@ -593,7 +619,8 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
sscreen->b.b.resource_create = r600_resource_create_common;
if (!r600_common_screen_init(&sscreen->b, ws) ||
!si_initialize_pipe_config(sscreen)) {
!si_initialize_pipe_config(sscreen) ||
!si_init_gs_info(sscreen)) {
FREE(sscreen);
return NULL;
}

2
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -42,6 +42,7 @@
#define SI_BASE_VERTEX_UNKNOWN INT_MIN
#define SI_RESTART_INDEX_UNKNOWN INT_MIN
#define SI_NUM_SMOOTH_AA_SAMPLES 8
#define SI_GS_PER_ES 128
/* Instruction cache. */
#define SI_CONTEXT_INV_ICACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
@ -85,6 +86,7 @@ struct si_compute;
struct si_screen {
struct r600_common_screen b;
unsigned gs_table_depth;
};
struct si_blend_color {

2
src/gallium/drivers/radeonsi/si_state.c
View file

@ -3264,7 +3264,7 @@ static void si_init_config(struct si_context *sctx)
si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
/* FIXME calculate these values somehow ??? */
si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);

4
src/gallium/drivers/radeonsi/si_state_draw.c
View file

@ -311,6 +311,10 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
if (ia_switch_on_eoi)
partial_es_wave = true;
/* GS requirement. */
if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
partial_es_wave = true;
/* Hw bug with single-primitive instances and SWITCH_ON_EOI
* on multi-SE chips. */
if (sctx->b.screen->info.max_se >= 2 && ia_switch_on_eoi &&