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intel/fs: Use CHV/BXT implementation of 64-bit MOV_INDIRECT on XeHP+.

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According to the hardware spec "Vx1 and VxH indirect addressing for
Float, Half-Float, Double-Float and Quad-Word data must not be used."

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10000>
This commit is contained in:
Francisco Jerez 2018-12-07 14:27:24 -08:00 • committed by Marge Bot
parent d57f3ced6c
commit 05cce1f97d
1 changed files with 1 additions and 1 deletions
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2
src/intel/compiler/brw_fs_generator.cpp
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@ -551,7 +551,7 @@ fs_generator::generate_mov_indirect(fs_inst *inst,
if (type_sz(reg.type) > 4 &&
((devinfo->ver == 7 && !devinfo->is_haswell) ||
devinfo->is_cherryview || gen_device_info_is_9lp(devinfo) ||
!devinfo->has_64bit_float)) {
!devinfo->has_64bit_float || devinfo->verx10 >= 125)) {
/* IVB has an issue (which we found empirically) where it reads two
* address register components per channel for indirectly addressed
* 64-bit sources.