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pan/nir: Add bifrost support to pan_nir_lower_tex()
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com> Reviewed-by: Lorenzo Rossi <lorenzo.rossi@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41036>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
2369808cd1
commit
05a066c921
1 changed files with 505 additions and 1 deletions
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@ -4,6 +4,7 @@
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*/
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#include "pan_nir.h"
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#include "bifrost/bifrost.h"
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#include "bifrost/valhall/valhall.h"
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#include "panfrost/model/pan_model.h"
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@ -171,6 +172,505 @@ scalar_as_imm_i4(nir_scalar s)
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_u; \
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})
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static bool
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bi_lower_texs(nir_builder *b, nir_tex_instr *tex, uint64_t gpu_id)
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{
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assert(tex->op == nir_texop_tex || tex->op == nir_texop_txl);
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if (tex->dest_type != nir_type_float32 &&
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tex->dest_type != nir_type_float16)
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return false;
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if (tex->is_shadow || tex->is_array)
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return false;
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switch (tex->sampler_dim) {
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case GLSL_SAMPLER_DIM_2D:
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case GLSL_SAMPLER_DIM_EXTERNAL:
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case GLSL_SAMPLER_DIM_RECT:
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break;
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case GLSL_SAMPLER_DIM_CUBE:
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/* LOD can't be specified with TEXS_CUBE */
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if (tex->op == nir_texop_txl)
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return false;
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break;
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default:
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return false;
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}
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nir_def *coord = NULL;
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for (unsigned i = 0; i < tex->num_srcs; ++i) {
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switch (tex->src[i].src_type) {
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case nir_tex_src_coord:
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coord = tex->src[i].src.ssa;
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break;
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case nir_tex_src_lod:
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if (!nir_src_is_zero(tex->src[i].src))
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return false;
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break;
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default:
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return false;
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}
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}
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/* Indices need to fit in provided bits */
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unsigned max_index = tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE ? 3 : 7;
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if (tex->sampler_index >= max_index || tex->texture_index >= max_index)
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return false;
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b->cursor = nir_before_instr(&tex->instr);
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struct pan_bi_tex_flags flags = {
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.explicit_lod = tex->op == nir_texop_txl,
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.sampler_idx = tex->sampler_index,
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.texture_idx = tex->texture_index,
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};
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nir_def *res;
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if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
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coord = build_cube_coord2_face(b, coord);
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res = nir_texs_cube_pan(b, tex->def.bit_size,
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nir_channel(b, coord, 0),
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nir_channel(b, coord, 1),
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nir_channel(b, coord, 2),
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.dest_type = tex->dest_type,
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.flags = PAN_AS_U32(flags));
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} else {
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res = nir_texs_2d_pan(b, tex->def.bit_size,
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nir_channel(b, coord, 0),
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nir_channel(b, coord, 1),
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.dest_type = tex->dest_type,
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.flags = PAN_AS_U32(flags));
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}
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nir_def_replace(&tex->def, res);
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return true;
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}
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static enum bifrost_texture_format_full
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bi_texture_format(nir_alu_type T, enum bi_clamp clamp)
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{
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switch (T) {
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case nir_type_float16:
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return BIFROST_TEXTURE_FORMAT_F16 + clamp;
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case nir_type_float32:
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return BIFROST_TEXTURE_FORMAT_F32 + clamp;
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case nir_type_uint16:
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return BIFROST_TEXTURE_FORMAT_U16;
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case nir_type_int16:
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return BIFROST_TEXTURE_FORMAT_S16;
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case nir_type_uint32:
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return BIFROST_TEXTURE_FORMAT_U32;
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case nir_type_int32:
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return BIFROST_TEXTURE_FORMAT_S32;
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default:
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UNREACHABLE("Invalid type for texturing");
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}
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}
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static unsigned
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bifrost_tex_format(enum glsl_sampler_dim dim)
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{
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switch (dim) {
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case GLSL_SAMPLER_DIM_1D:
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case GLSL_SAMPLER_DIM_BUF:
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return 1;
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case GLSL_SAMPLER_DIM_2D:
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case GLSL_SAMPLER_DIM_MS:
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case GLSL_SAMPLER_DIM_EXTERNAL:
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case GLSL_SAMPLER_DIM_RECT:
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case GLSL_SAMPLER_DIM_SUBPASS:
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case GLSL_SAMPLER_DIM_SUBPASS_MS:
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return 2;
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case GLSL_SAMPLER_DIM_3D:
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return 3;
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case GLSL_SAMPLER_DIM_CUBE:
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return 0;
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default:
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UNREACHABLE("Unknown sampler dim type\n");
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}
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}
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static nir_def *
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build_bi_texc(nir_builder *b, nir_alu_type dest_type,
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nir_def *tex_idx, nir_def *samp_idx,
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enum glsl_sampler_dim dim,
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nir_def *coord_xy,
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struct bifrost_texture_operation desc,
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bool explicit_lod,
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nir_def **sr, unsigned sr_count)
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{
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const struct pan_bi_tex_flags flags = {
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.explicit_lod = explicit_lod,
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};
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desc.dimension = bifrost_tex_format(dim);
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desc.format = bi_texture_format(dest_type, BI_CLAMP_NONE);
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assert(coord_xy->bit_size == 32);
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nir_def *coord_x = nir_channel(b, coord_xy, 0);
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nir_def *coord_y = coord_xy->num_components > 1 ?
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nir_channel(b, coord_xy, 1) : nir_imm_int(b, 0);
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uint32_t imm_tex_idx = nir_scalar_is_const(nir_get_scalar(tex_idx, 0))
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? nir_scalar_as_uint(nir_get_scalar(tex_idx, 0))
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: UINT32_MAX;
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uint32_t imm_samp_idx = nir_scalar_is_const(nir_get_scalar(samp_idx, 0))
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? nir_scalar_as_uint(nir_get_scalar(samp_idx, 0))
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: UINT32_MAX;
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if (imm_tex_idx < 128 && imm_samp_idx < 16) {
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desc.immediate_indices = true;
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desc.sampler_index_or_mode = imm_samp_idx;
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desc.index = imm_tex_idx;
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tex_idx = samp_idx = NULL;
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} else if (imm_tex_idx == imm_samp_idx && imm_tex_idx < 128) {
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desc.immediate_indices = false;
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desc.sampler_index_or_mode = BIFROST_INDEX_IMMEDIATE_SHARED |
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(BIFROST_TEXTURE_OPERATION_SINGLE << 2);
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desc.index = imm_tex_idx;
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tex_idx = samp_idx = NULL;
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} else if (imm_tex_idx < 128) {
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desc.immediate_indices = false;
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desc.sampler_index_or_mode = BIFROST_INDEX_IMMEDIATE_TEXTURE |
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(BIFROST_TEXTURE_OPERATION_SINGLE << 2);
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desc.index = imm_tex_idx;
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tex_idx = NULL;
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} else if (imm_samp_idx < 16) {
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desc.immediate_indices = false;
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desc.sampler_index_or_mode = BIFROST_INDEX_IMMEDIATE_SAMPLER |
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(BIFROST_TEXTURE_OPERATION_SINGLE << 2);
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desc.index = imm_samp_idx;
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samp_idx = NULL;
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} else {
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desc.immediate_indices = false;
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desc.sampler_index_or_mode = BIFROST_INDEX_REGISTER |
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(BIFROST_TEXTURE_OPERATION_SINGLE << 2);
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}
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/* Sampler and texture go at the end. (See also bifrost_tex_sreg.) Extend
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* sr for sampler and texture if needed.
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*/
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assert(sr_count <= 6);
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nir_def *sr_tmp[8];
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if (samp_idx || tex_idx) {
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for (unsigned i = 0; i < sr_count; i++)
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sr_tmp[i] = sr[i];
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if (samp_idx)
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sr_tmp[sr_count++] = samp_idx;
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if (tex_idx)
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sr_tmp[sr_count++] = tex_idx;
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sr = sr_tmp;
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}
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if (sr_count == 0) {
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return nir_texc0_pan(b, nir_alu_type_get_type_size(dest_type),
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coord_x, coord_y, nir_imm_int(b, desc.packed),
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.dest_type = dest_type,
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.flags = PAN_AS_U32(flags));
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} else if (sr_count <= 4) {
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return nir_texc1_pan(b, nir_alu_type_get_type_size(dest_type),
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coord_x, coord_y, nir_imm_int(b, desc.packed),
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nir_vec(b, sr, sr_count),
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.dest_type = dest_type,
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.flags = PAN_AS_U32(flags));
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} else {
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return nir_texc2_pan(b, nir_alu_type_get_type_size(dest_type),
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coord_x, coord_y, nir_imm_int(b, desc.packed),
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nir_vec(b, sr, 4),
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nir_vec(b, sr + 4, sr_count - 4),
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.dest_type = dest_type,
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.flags = PAN_AS_U32(flags));
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}
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}
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static nir_def *
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build_bi_gradient_desc(nir_builder *b,
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nir_def *tex_idx, nir_def *samp_idx,
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enum glsl_sampler_dim dim,
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nir_def *ddx, nir_def *ddy)
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{
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struct bifrost_texture_operation desc = {
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.op = BIFROST_TEX_OP_GRDESC_DER,
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.offset_or_bias_disable = true,
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.shadow_or_clamp_disable = true,
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.mask = 0xf,
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};
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nir_def *sr[4];
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unsigned sr_count = 0;
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nir_def *ddx_xy = nir_trim_vector(b, ddx, MIN2(ddx->num_components, 2));
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for (unsigned i = 2; i < ddx->num_components; i++)
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sr[sr_count++] = nir_channel(b, ddx, i);
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for (unsigned i = 0; i < ddy->num_components; i++)
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sr[sr_count++] = nir_channel(b, ddy, i);
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assert(sr_count <= ARRAY_SIZE(sr));
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return build_bi_texc(b, nir_type_float32, tex_idx, samp_idx,
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dim, ddx_xy, desc, true, sr, sr_count);
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}
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static enum bifrost_tex_op
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bi_tex_op(nir_texop op)
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{
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switch (op) {
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case nir_texop_tex:
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case nir_texop_txb:
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case nir_texop_txl:
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case nir_texop_txd:
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return BIFROST_TEX_OP_TEX;
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case nir_texop_txf:
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case nir_texop_txf_ms:
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case nir_texop_tg4:
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return BIFROST_TEX_OP_FETCH;
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case nir_texop_lod:
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return BIFROST_TEX_OP_GRDESC;
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default:
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UNREACHABLE("Unhandled Bifrost texture op");
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}
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}
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/* Data registers required by texturing in the order they appear. All are
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* optional, the texture operation descriptor determines which are present.
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* Note since 3D arrays are not permitted at an API level, Z_COORD and
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* ARRAY/SHADOW are exlusive, so TEXC in practice reads at most 8 registers
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*/
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enum bifrost_tex_sreg {
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BI_TEX_SR_Z_COORD = 0,
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BI_TEX_SR_Y_DELTAS,
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BI_TEX_SR_LOD,
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BI_TEX_SR_GRDESC0,
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BI_TEX_SR_GRDESC1,
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BI_TEX_SR_SHADOW,
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BI_TEX_SR_ARRAY,
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BI_TEX_SR_OFFSET,
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BI_TEX_SR_SAMPLER,
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BI_TEX_SR_TEXTURE,
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BI_TEX_SR_COUNT,
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};
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static bool
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bi_lower_tex(nir_builder *b, nir_tex_instr *tex, uint64_t gpu_id)
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{
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/* If txf is used, we assume there is a valid sampler bound at index 0. Use
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* it for txf operations, since there may be no other valid samplers. This is
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* a workaround: txf does not require a sampler in NIR (so sampler_index is
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* undefined) but we need one in the hardware. This is ABI with the driver.
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*/
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if (!nir_tex_instr_need_sampler(tex))
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tex->sampler_index = 0;
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struct bifrost_texture_operation desc = {
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.mask = nir_def_components_read(&tex->def),
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};
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b->cursor = nir_before_instr(&tex->instr);
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struct tex_srcs srcs = steal_tex_srcs(b, tex);
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nir_def *coord_xy = NULL;
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nir_def *sr[BI_TEX_SR_COUNT] = {};
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const unsigned coord_comps = tex->coord_components - tex->is_array;
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if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
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/* texelFetch() does not support cubes */
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assert(tex->op != nir_texop_txf && tex->op != nir_texop_txf_ms);
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assert(coord_comps == 3);
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coord_xy = build_cube_desc(b, srcs.coord);
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} else {
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coord_xy = nir_trim_vector(b, srcs.coord, MIN2(coord_comps, 2));
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if (tex->sampler_dim == GLSL_SAMPLER_DIM_3D)
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sr[BI_TEX_SR_Z_COORD] = nir_channel(b, srcs.coord, 2);
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}
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if (tex->is_array) {
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nir_def *arr_idx = nir_channel(b, srcs.coord, coord_comps);
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/* OpenGL ES 3.2 specification section 8.14.2 ("Coordinate Wrapping and
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* Texel Selection") defines the layer to be taken from clamp(RNE(r),
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* 0, dt - 1). So we use round RTE, clamping is handled at the data
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* structure level
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*/
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if (tex->op != nir_texop_txf && tex->op != nir_texop_txf_ms)
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arr_idx = nir_f2u32_rtne(b, arr_idx);
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sr[BI_TEX_SR_ARRAY] = arr_idx;
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desc.array = true;
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}
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if (tex->op == nir_texop_txf ||
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tex->op == nir_texop_txf_ms ||
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tex->op == nir_texop_tg4) {
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desc.op = BIFROST_TEX_OP_FETCH;
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/* FETCH always takes an LOD as an 8.8 fixed-point value. GLSL and
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* SPIR-V give us an integer, so we have to convert.
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*/
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if (srcs.lod)
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sr[BI_TEX_SR_LOD] = nir_ishl_imm(b, srcs.lod, 8);
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else
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sr[BI_TEX_SR_LOD] = nir_imm_int(b, 0);
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if (tex->op == nir_texop_tg4) {
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desc.lod_or_fetch = BIFROST_TEXTURE_FETCH_GATHER4_R +
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tex->component;
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} else {
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desc.lod_or_fetch = BIFROST_TEXTURE_FETCH_TEXEL;
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}
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} else {
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desc.op = BIFROST_TEX_OP_TEX;
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if (srcs.lod) {
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if (nir_scalar_is_zero(nir_get_scalar(srcs.lod, 0))) {
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desc.lod_or_fetch = BIFROST_LOD_MODE_ZERO;
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} else {
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desc.lod_or_fetch = BIFROST_LOD_MODE_EXPLICIT;
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sr[BI_TEX_SR_LOD] = nir_u2u32(b, build_sfixed_8_8(b, srcs.lod));
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}
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} else if (srcs.min_lod || srcs.bias) {
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desc.lod_or_fetch = BIFROST_LOD_MODE_BIAS;
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sr[BI_TEX_SR_LOD] = build_lod_bias_clamp(b, srcs.bias, srcs.min_lod);
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} else if (srcs.ddx || srcs.ddy) {
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desc.lod_or_fetch = BIFROST_LOD_MODE_GRDESC;
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nir_def *grdesc = build_bi_gradient_desc(b, srcs.tex_h, srcs.samp_h,
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tex->sampler_dim,
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srcs.ddx, srcs.ddy);
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sr[BI_TEX_SR_GRDESC0] = nir_channel(b, grdesc, 0);
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sr[BI_TEX_SR_GRDESC1] = nir_channel(b, grdesc, 1);
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} else {
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desc.lod_or_fetch = BIFROST_LOD_MODE_COMPUTE;
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}
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}
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if (srcs.z_cmpr) {
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sr[BI_TEX_SR_SHADOW] = srcs.z_cmpr;
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desc.shadow_or_clamp_disable = true;
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}
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if (srcs.offset || srcs.ms_idx) {
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/* The hardware specifies the offset, MS index, and lod (for TXF) in a
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* u8vec4 <off_s, off_t, off_r, ms_idx>.
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*/
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nir_scalar comps[4] = { };
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if (srcs.offset) {
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assert(srcs.offset->num_components == coord_comps);
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for (unsigned i = 0; i < coord_comps; i++)
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comps[i] = nir_get_scalar(srcs.offset, i);
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}
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if (srcs.ms_idx)
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comps[3] = nir_get_scalar(srcs.ms_idx, 0);
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||||
/* Fill in the rest with zero */
|
||||
for (unsigned i = 0; i < 4; i++) {
|
||||
if (!comps[i].def)
|
||||
comps[i] = nir_get_scalar(nir_imm_int(b, 0), 0);
|
||||
}
|
||||
|
||||
sr[BI_TEX_SR_OFFSET] =
|
||||
nir_pack_32_4x8(b, nir_i2i8(b, nir_vec_scalars(b, comps, 4)));
|
||||
desc.offset_or_bias_disable = true;
|
||||
}
|
||||
|
||||
unsigned sr_count = 0;
|
||||
for (unsigned i = 0; i < BI_TEX_SR_COUNT; i++) {
|
||||
if (sr[i])
|
||||
sr[sr_count++] = sr[i];
|
||||
}
|
||||
|
||||
const bool explicit_lod = !nir_tex_instr_has_implicit_derivative(tex);
|
||||
nir_def *res = build_bi_texc(b, tex->dest_type | tex->def.bit_size,
|
||||
srcs.tex_h, srcs.samp_h, tex->sampler_dim,
|
||||
coord_xy, desc, explicit_lod, sr, sr_count);
|
||||
|
||||
/* For shadow, we may have to trim the result */
|
||||
if (tex->def.num_components < res->num_components)
|
||||
res = nir_trim_vector(b, res, tex->def.num_components);
|
||||
|
||||
nir_def_replace(&tex->def, res);
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool
|
||||
bi_lower_lod(nir_builder *b, nir_tex_instr *tex, uint64_t gpu_id)
|
||||
{
|
||||
b->cursor = nir_before_instr(&tex->instr);
|
||||
struct tex_srcs srcs = steal_tex_srcs(b, tex);
|
||||
|
||||
struct bifrost_texture_operation desc = {
|
||||
.op = BIFROST_TEX_OP_GRDESC,
|
||||
.mask = 1,
|
||||
};
|
||||
|
||||
nir_def *coord_xy, *coord_z = NULL;
|
||||
const unsigned coord_comps = tex->coord_components;
|
||||
if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
|
||||
coord_xy = build_cube_desc(b, srcs.coord);
|
||||
} else {
|
||||
coord_xy = nir_trim_vector(b, srcs.coord, MIN2(coord_comps, 2));
|
||||
if (tex->sampler_dim == GLSL_SAMPLER_DIM_3D)
|
||||
coord_z = nir_channel(b, srcs.coord, 2);
|
||||
}
|
||||
|
||||
nir_def *comps[2];
|
||||
for (unsigned i = 0; i < 2; i++) {
|
||||
desc.shadow_or_clamp_disable = i != 0;
|
||||
nir_def *grdesc = build_bi_texc(b, nir_type_float32,
|
||||
srcs.tex_h, srcs.samp_h,
|
||||
tex->sampler_dim, coord_xy, desc,
|
||||
false, &coord_z, coord_z ? 1 : 0);
|
||||
|
||||
nir_def *lod_i16 = nir_unpack_32_2x16_split_x(b, grdesc);
|
||||
|
||||
assert(tex->dest_type == nir_type_float32);
|
||||
nir_def *lod = nir_i2f32(b, lod_i16);
|
||||
|
||||
lod = nir_fdiv_imm(b, lod, 256.0);
|
||||
if (i == 0)
|
||||
lod = nir_fround_even(b, lod);
|
||||
|
||||
comps[i] = lod;
|
||||
}
|
||||
|
||||
nir_def_replace(&tex->def, nir_vec2(b, comps[0], comps[1]));
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool
|
||||
bi_lower_tex_instr(nir_builder *b, nir_tex_instr *tex, void *cb_data)
|
||||
{
|
||||
uint64_t gpu_id = *(uint64_t *)cb_data;
|
||||
|
||||
switch (tex->op) {
|
||||
case nir_texop_tex:
|
||||
case nir_texop_txl:
|
||||
if (bi_lower_texs(b, tex, gpu_id))
|
||||
return true;
|
||||
|
||||
FALLTHROUGH;
|
||||
|
||||
case nir_texop_txb:
|
||||
case nir_texop_txd:
|
||||
case nir_texop_txf:
|
||||
case nir_texop_txf_ms:
|
||||
case nir_texop_tg4:
|
||||
return bi_lower_tex(b, tex, gpu_id);
|
||||
|
||||
case nir_texop_lod:
|
||||
return bi_lower_lod(b, tex, gpu_id);
|
||||
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static nir_def *
|
||||
va_tex_handle(nir_builder *b, nir_def *tex_h, nir_def *samp_h)
|
||||
{
|
||||
|
|
@ -498,7 +998,11 @@ pan_nir_lower_tex(nir_shader *nir, uint64_t gpu_id)
|
|||
return nir_shader_tex_pass(nir, va_lower_tex_instr,
|
||||
nir_metadata_control_flow,
|
||||
&gpu_id);
|
||||
} else if (pan_arch(gpu_id) >= 6) {
|
||||
return nir_shader_tex_pass(nir, bi_lower_tex_instr,
|
||||
nir_metadata_control_flow,
|
||||
&gpu_id);
|
||||
} else {
|
||||
UNREACHABLE("Midgard and Bifrost are not supported by this pass");
|
||||
UNREACHABLE("Midgard is not supported by this pass");
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue