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radeon/llvm: Add helper function for getting sub reg indices
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1a25ebe3ce
commit
0588298575
3 changed files with 19 additions and 6 deletions
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@ -50,16 +50,13 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const
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{
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unsigned subRegMap[4] = {AMDGPU::sel_x, AMDGPU::sel_y,
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AMDGPU::sel_z, AMDGPU::sel_w};
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if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
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&& AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
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for (unsigned i = 0; i < 4; i++) {
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unsigned SubRegIndex = RI.getSubRegFromChannel(i);
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BuildMI(MBB, MI, DL, get(AMDGPU::MOV))
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.addReg(RI.getSubReg(DestReg, subRegMap[i]), RegState::Define)
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.addReg(RI.getSubReg(SrcReg, subRegMap[i]))
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.addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define)
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.addReg(RI.getSubReg(SrcReg, SubRegIndex))
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.addReg(0) // PREDICATE_BIT
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.addReg(DestReg, RegState::Define | RegState::Implicit);
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}
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@ -112,4 +112,16 @@ const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
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case MVT::i32: return AMDGPU::R600_TReg32RegisterClass;
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}
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}
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unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) const
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{
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switch (Channel) {
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default: assert(!"Invalid channel index"); return 0;
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case 0: return AMDGPU::sel_x;
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case 1: return AMDGPU::sel_y;
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case 2: return AMDGPU::sel_z;
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case 3: return AMDGPU::sel_w;
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}
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}
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#include "R600HwRegInfo.include"
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@ -46,6 +46,10 @@ struct R600RegisterInfo : public AMDGPURegisterInfo
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/// type to use in the CFGStructurizer
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virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
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/// getSubRegFromChannel - Return the sub reg enum value for the given
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/// Channel (e.g. getSubRegFromChannel(0) -> AMDGPU::sel_x)
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unsigned getSubRegFromChannel(unsigned Channel) const;
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private:
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/// getHWRegIndexGen - Generated function returns a register's encoding
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unsigned getHWRegIndexGen(unsigned reg) const;
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