radeon/llvm: Add helper function for getting sub reg indices

This commit is contained in:
Tom Stellard 2012-08-20 21:08:03 +00:00
parent 1a25ebe3ce
commit 0588298575
3 changed files with 19 additions and 6 deletions

View file

@ -50,16 +50,13 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const
{
unsigned subRegMap[4] = {AMDGPU::sel_x, AMDGPU::sel_y,
AMDGPU::sel_z, AMDGPU::sel_w};
if (AMDGPU::R600_Reg128RegClass.contains(DestReg)
&& AMDGPU::R600_Reg128RegClass.contains(SrcReg)) {
for (unsigned i = 0; i < 4; i++) {
unsigned SubRegIndex = RI.getSubRegFromChannel(i);
BuildMI(MBB, MI, DL, get(AMDGPU::MOV))
.addReg(RI.getSubReg(DestReg, subRegMap[i]), RegState::Define)
.addReg(RI.getSubReg(SrcReg, subRegMap[i]))
.addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define)
.addReg(RI.getSubReg(SrcReg, SubRegIndex))
.addReg(0) // PREDICATE_BIT
.addReg(DestReg, RegState::Define | RegState::Implicit);
}

View file

@ -112,4 +112,16 @@ const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
case MVT::i32: return AMDGPU::R600_TReg32RegisterClass;
}
}
unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) const
{
switch (Channel) {
default: assert(!"Invalid channel index"); return 0;
case 0: return AMDGPU::sel_x;
case 1: return AMDGPU::sel_y;
case 2: return AMDGPU::sel_z;
case 3: return AMDGPU::sel_w;
}
}
#include "R600HwRegInfo.include"

View file

@ -46,6 +46,10 @@ struct R600RegisterInfo : public AMDGPURegisterInfo
/// type to use in the CFGStructurizer
virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
/// getSubRegFromChannel - Return the sub reg enum value for the given
/// Channel (e.g. getSubRegFromChannel(0) -> AMDGPU::sel_x)
unsigned getSubRegFromChannel(unsigned Channel) const;
private:
/// getHWRegIndexGen - Generated function returns a register's encoding
unsigned getHWRegIndexGen(unsigned reg) const;