From 0580d4c1a25b75616d1b8732624bf63a27a929a9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 20 Mar 2021 01:00:11 -0400 Subject: [PATCH] radeonsi: enable HTILE with mipmapping on gfx9+ Everything seems to be there except fast clears. Acked-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_blit.c | 2 ++ src/gallium/drivers/radeonsi/si_clear.c | 7 ++++++- src/gallium/drivers/radeonsi/si_pipe.h | 2 +- src/gallium/drivers/radeonsi/si_texture.c | 8 ++++++-- 4 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c index b5cf10913c0..8c1dca6c807 100644 --- a/src/gallium/drivers/radeonsi/si_blit.c +++ b/src/gallium/drivers/radeonsi/si_blit.c @@ -374,6 +374,8 @@ static void si_decompress_depth(struct si_context *sctx, struct si_texture *tex, * the decompression is much worse. */ if (has_htile && !tc_compat_htile && + /* We can only transition the whole buffer in one clear, so no mipmapping: */ + tex->buffer.b.b.last_level == 0 && tex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE && (inplace_planes & PIPE_MASK_Z || !tex->htile_stencil_disabled)) tex->enable_tc_compatible_htile_next_clear = true; diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index 756a7bde44e..56d486afc53 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -646,7 +646,9 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers, } if (zstex && zsbuf->u.tex.first_layer == 0 && - zsbuf->u.tex.last_layer == util_max_layer(&zstex->buffer.b.b, 0)) { + zsbuf->u.tex.last_layer == util_max_layer(&zstex->buffer.b.b, 0) && + /* TODO: enable fast clear for other mipmap levels */ + zsbuf->u.tex.level == 0) { /* See whether we should enable TC-compatible HTILE. */ if (zstex->enable_tc_compatible_htile_next_clear && !zstex->tc_compatible_htile && @@ -655,6 +657,9 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers, ((buffers & PIPE_CLEAR_DEPTHSTENCIL) == PIPE_CLEAR_DEPTHSTENCIL || (buffers & PIPE_CLEAR_DEPTH && (!zstex->surface.has_stencil || zstex->htile_stencil_disabled)))) { + /* The conversion from TC-incompatible to TC-compatible can only be done in one clear. */ + assert(zstex->buffer.b.b.last_level == 0); + /* Enable TC-compatible HTILE. */ zstex->enable_tc_compatible_htile_next_clear = false; zstex->tc_compatible_htile = true; diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 17b61572240..f610e5460d4 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -1840,7 +1840,7 @@ static inline bool si_htile_enabled(struct si_texture *tex, unsigned level, unsi if (zs_mask == PIPE_MASK_S && tex->htile_stencil_disabled) return false; - return tex->surface.htile_offset && level == 0; + return tex->surface.htile_offset && level < tex->surface.num_htile_levels; } static inline bool vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level, diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index 386a5e5262d..7797f6cb83c 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -929,8 +929,12 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen, * GFX9 and later use the same tiling for both, so TC-compatible HTILE can be * enabled on demand. */ - tex->tc_compatible_htile = sscreen->info.chip_class == GFX8 && - tex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE; + tex->tc_compatible_htile = (sscreen->info.chip_class == GFX8 && + tex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE) || + /* Mipmapping always starts TC-compatible. */ + (sscreen->info.chip_class >= GFX8 && + tex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE && + tex->buffer.b.b.last_level > 0); /* TC-compatible HTILE: * - GFX8 only supports Z32_FLOAT.