fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-25 04:20:08 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

i965: Drop redundant check for non-tiled depth buffer

Browse source 
Depth buffers are always Y-tiled. In brw_miptree_choose_tiling()
driver opts to use linear buffers for small and 1D but this does
not apply for depth - GL_DEPTH_COMPONENT and GL_DEPTH_STENCIL_EXT
are considered first.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
This commit is contained in:
Topi Pohjolainen 2017-06-07 11:00:43 +03:00
parent c4ac0d4949
commit 05232a2361
2 changed files with 2 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/mesa/drivers/dri/i965/brw_misc_state.c
View file

@ -383,8 +383,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH((depth_mt ? depth_mt->surf.row_pitch - 1 : 0) |
(depthbuffer_format << 18) |
(BRW_TILEWALK_YMAJOR << 26) |
((depth_mt ? depth_mt->surf.tiling != ISL_TILING_LINEAR : 1)
<< 27) |
(1 << 27) |
(depth_surface_type << 29));
if (depth_mt) {

3
src/mesa/drivers/dri/i965/gen6_depth_state.c
View file

@ -121,8 +121,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
((enable_hiz_ss ? 1 : 0) << 21) | /* separate stencil enable */
((enable_hiz_ss ? 1 : 0) << 22) | /* hiz enable */
(BRW_TILEWALK_YMAJOR << 26) |
((depth_mt ? depth_mt->surf.tiling != ISL_TILING_LINEAR : 1)
<< 27) |
(1 << 27) |
(surftype << 29));
/* 3DSTATE_DEPTH_BUFFER dw2 */