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panvk: Move the linking bits to panvk_shader
Needed if we support late linking which is required for VK_EXT_shader_object. We also stop pretending the linking is generic and reflect the fact we always link vertex with fragment shaders. Signed-off-by: Mary Guillemard <mary.guillemard@collabora.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29161>
This commit is contained in:
parent
9c39185e20
commit
05020699b9
5 changed files with 229 additions and 207 deletions
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@ -29,11 +29,6 @@
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struct panvk_pipeline_shader {
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struct panvk_shader *base;
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struct {
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struct panvk_priv_mem attribs;
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unsigned buf_strides[PANVK_VARY_BUF_MAX];
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} varyings;
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struct pan_shader_info info;
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};
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@ -57,6 +52,7 @@ struct panvk_graphics_pipeline {
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struct panvk_pipeline_shader vs;
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struct panvk_pipeline_shader fs;
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struct panvk_shader_link link;
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struct {
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struct vk_dynamic_graphics_state dynamic;
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@ -89,203 +89,6 @@ cleanup_pipeline_shader(struct panvk_pipeline *pipeline,
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panvk_per_arch(shader_destroy)(dev, pshader->base, alloc);
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}
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static mali_pixel_format
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get_varying_format(gl_shader_stage stage, gl_varying_slot loc,
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enum pipe_format pfmt)
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{
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switch (loc) {
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case VARYING_SLOT_PNTC:
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case VARYING_SLOT_PSIZ:
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#if PAN_ARCH <= 6
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return (MALI_R16F << 12) | panfrost_get_default_swizzle(1);
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#else
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return (MALI_R16F << 12) | MALI_RGB_COMPONENT_ORDER_R000;
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#endif
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case VARYING_SLOT_POS:
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#if PAN_ARCH <= 6
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return (MALI_SNAP_4 << 12) | panfrost_get_default_swizzle(4);
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#else
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return (MALI_SNAP_4 << 12) | MALI_RGB_COMPONENT_ORDER_RGBA;
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#endif
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default:
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assert(pfmt != PIPE_FORMAT_NONE);
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return GENX(panfrost_format_from_pipe_format)(pfmt)->hw;
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}
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}
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struct varyings_info {
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enum pipe_format fmts[VARYING_SLOT_MAX];
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BITSET_DECLARE(active, VARYING_SLOT_MAX);
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};
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static void
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collect_varyings_info(const struct pan_shader_varying *varyings,
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unsigned varying_count, struct varyings_info *info)
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{
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for (unsigned i = 0; i < varying_count; i++) {
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gl_varying_slot loc = varyings[i].location;
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if (varyings[i].format == PIPE_FORMAT_NONE)
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continue;
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info->fmts[loc] = varyings[i].format;
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BITSET_SET(info->active, loc);
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}
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}
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static inline enum panvk_varying_buf_id
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varying_buf_id(gl_varying_slot loc)
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{
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switch (loc) {
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case VARYING_SLOT_POS:
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return PANVK_VARY_BUF_POSITION;
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case VARYING_SLOT_PSIZ:
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return PANVK_VARY_BUF_PSIZ;
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default:
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return PANVK_VARY_BUF_GENERAL;
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}
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}
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static mali_pixel_format
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varying_format(gl_varying_slot loc, enum pipe_format pfmt)
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{
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switch (loc) {
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case VARYING_SLOT_PNTC:
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case VARYING_SLOT_PSIZ:
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#if PAN_ARCH <= 6
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return (MALI_R16F << 12) | panfrost_get_default_swizzle(1);
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#else
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return (MALI_R16F << 12) | MALI_RGB_COMPONENT_ORDER_R000;
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#endif
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case VARYING_SLOT_POS:
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#if PAN_ARCH <= 6
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return (MALI_SNAP_4 << 12) | panfrost_get_default_swizzle(4);
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#else
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return (MALI_SNAP_4 << 12) | MALI_RGB_COMPONENT_ORDER_RGBA;
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#endif
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default:
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return GENX(panfrost_format_from_pipe_format)(pfmt)->hw;
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}
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}
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static struct panvk_priv_mem
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emit_varying_attrs(struct panvk_pool *desc_pool,
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const struct pan_shader_varying *varyings,
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unsigned varying_count, const struct varyings_info *info,
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unsigned *buf_offsets)
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{
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unsigned attr_count = BITSET_COUNT(info->active);
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struct panvk_priv_mem mem =
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panvk_pool_alloc_desc_array(desc_pool, attr_count, ATTRIBUTE);
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struct mali_attribute_packed *attrs = panvk_priv_mem_host_addr(mem);
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unsigned attr_idx = 0;
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for (unsigned i = 0; i < varying_count; i++) {
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pan_pack(&attrs[attr_idx++], ATTRIBUTE, cfg) {
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gl_varying_slot loc = varyings[i].location;
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enum pipe_format pfmt = varyings[i].format != PIPE_FORMAT_NONE
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? info->fmts[loc]
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: PIPE_FORMAT_NONE;
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if (pfmt == PIPE_FORMAT_NONE) {
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#if PAN_ARCH >= 7
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cfg.format = (MALI_CONSTANT << 12) | MALI_RGB_COMPONENT_ORDER_0000;
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#else
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cfg.format = (MALI_CONSTANT << 12) | PAN_V6_SWIZZLE(0, 0, 0, 0);
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#endif
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} else {
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cfg.buffer_index = varying_buf_id(loc);
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cfg.offset = buf_offsets[loc];
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cfg.format = varying_format(loc, info->fmts[loc]);
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}
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cfg.offset_enable = false;
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}
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}
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return mem;
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}
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static void
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link_shaders(struct panvk_graphics_pipeline *pipeline,
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struct panvk_pipeline_shader *stage,
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struct panvk_pipeline_shader *next_stage)
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{
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struct panvk_device *dev = to_panvk_device(pipeline->base.base.device);
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BITSET_DECLARE(active_attrs, VARYING_SLOT_MAX) = {0};
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unsigned buf_strides[PANVK_VARY_BUF_MAX] = {0};
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unsigned buf_offsets[VARYING_SLOT_MAX] = {0};
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struct varyings_info out_vars = {0};
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struct varyings_info in_vars = {0};
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unsigned loc;
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collect_varyings_info(stage->info.varyings.output,
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stage->info.varyings.output_count, &out_vars);
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collect_varyings_info(next_stage->info.varyings.input,
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next_stage->info.varyings.input_count, &in_vars);
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BITSET_OR(active_attrs, in_vars.active, out_vars.active);
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/* Handle the position and point size buffers explicitly, as they are
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* passed through separate buffer pointers to the tiler job.
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*/
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if (next_stage->info.stage == MESA_SHADER_FRAGMENT) {
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if (BITSET_TEST(out_vars.active, VARYING_SLOT_POS)) {
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buf_strides[PANVK_VARY_BUF_POSITION] = sizeof(float) * 4;
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BITSET_CLEAR(active_attrs, VARYING_SLOT_POS);
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}
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if (BITSET_TEST(out_vars.active, VARYING_SLOT_PSIZ)) {
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buf_strides[PANVK_VARY_BUF_PSIZ] = sizeof(uint16_t);
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BITSET_CLEAR(active_attrs, VARYING_SLOT_PSIZ);
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}
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}
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BITSET_FOREACH_SET(loc, active_attrs, VARYING_SLOT_MAX) {
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/* We expect stage to write to all inputs read by next_stage, and
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* next_stage to read all inputs written by stage. If that's not the
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* case, we keep PIPE_FORMAT_NONE to reflect the fact we should use a
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* sink attribute (writes are discarded, reads return zeros).
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*/
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if (in_vars.fmts[loc] == PIPE_FORMAT_NONE ||
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out_vars.fmts[loc] == PIPE_FORMAT_NONE) {
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in_vars.fmts[loc] = PIPE_FORMAT_NONE;
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out_vars.fmts[loc] = PIPE_FORMAT_NONE;
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continue;
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}
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unsigned out_size = util_format_get_blocksize(out_vars.fmts[loc]);
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unsigned buf_idx = varying_buf_id(loc);
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/* Always trust the 'next_stage' input format, so we can:
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* - discard components that are never read
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* - use float types for interpolated fragment shader inputs
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* - use fp16 for floats with mediump
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* - make sure components that are not written by 'stage' are set to zero
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*/
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out_vars.fmts[loc] = in_vars.fmts[loc];
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/* Special buffers are handled explicitly before this loop, everything
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* else should be laid out in the general varying buffer.
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*/
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assert(buf_idx == PANVK_VARY_BUF_GENERAL);
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/* Keep things aligned a 32-bit component. */
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buf_offsets[loc] = buf_strides[buf_idx];
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buf_strides[buf_idx] += ALIGN_POT(out_size, 4);
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}
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stage->varyings.attribs = emit_varying_attrs(
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&dev->mempools.rw, stage->info.varyings.output,
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stage->info.varyings.output_count, &out_vars, buf_offsets);
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next_stage->varyings.attribs = emit_varying_attrs(
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&dev->mempools.rw, next_stage->info.varyings.input,
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next_stage->info.varyings.input_count, &in_vars, buf_offsets);
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memcpy(stage->varyings.buf_strides, buf_strides,
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sizeof(stage->varyings.buf_strides));
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memcpy(next_stage->varyings.buf_strides, buf_strides,
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sizeof(next_stage->varyings.buf_strides));
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}
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static VkResult
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panvk_graphics_pipeline_create(struct panvk_device *dev,
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struct vk_pipeline_cache *cache,
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@ -344,7 +147,8 @@ panvk_graphics_pipeline_create(struct panvk_device *dev,
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return result;
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}
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link_shaders(gfx_pipeline, &gfx_pipeline->vs, &gfx_pipeline->fs);
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panvk_per_arch(link_shaders)(&dev->mempools.rw, gfx_pipeline->vs.base,
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gfx_pipeline->fs.base, &gfx_pipeline->link);
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return VK_SUCCESS;
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}
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@ -445,6 +249,7 @@ panvk_per_arch(DestroyPipeline)(VkDevice _device, VkPipeline _pipeline,
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struct panvk_graphics_pipeline *gfx_pipeline =
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panvk_pipeline_to_graphics_pipeline(pipeline);
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panvk_shader_link_cleanup(&device->mempools.rw, &gfx_pipeline->link);
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cleanup_pipeline_shader(pipeline, &gfx_pipeline->vs, pAllocator);
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cleanup_pipeline_shader(pipeline, &gfx_pipeline->fs, pAllocator);
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} else {
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@ -511,7 +511,7 @@ panvk_draw_prepare_varyings(struct panvk_cmd_buffer *cmdbuf,
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mali_ptr psiz_buf = 0;
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for (unsigned i = 0; i < PANVK_VARY_BUF_MAX; i++) {
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unsigned buf_size = vertex_count * pipeline->vs.varyings.buf_strides[i];
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unsigned buf_size = vertex_count * pipeline->link.buf_strides[i];
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mali_ptr buf_addr =
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buf_size
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? pan_pool_alloc_aligned(&cmdbuf->varying_pool.base, buf_size, 64)
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@ -519,7 +519,7 @@ panvk_draw_prepare_varyings(struct panvk_cmd_buffer *cmdbuf,
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: 0;
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pan_pack(&buf_descs[i], ATTRIBUTE_BUFFER, cfg) {
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cfg.stride = pipeline->vs.varyings.buf_strides[i];
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cfg.stride = pipeline->link.buf_strides[i];
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cfg.size = buf_size;
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cfg.pointer = buf_addr;
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}
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@ -544,8 +544,8 @@ panvk_draw_prepare_varyings(struct panvk_cmd_buffer *cmdbuf,
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draw->line_width = 1.0f;
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draw->varying_bufs = bufs.gpu;
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draw->vs.varyings = panvk_priv_mem_dev_addr(pipeline->vs.varyings.attribs);
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draw->fs.varyings = panvk_priv_mem_dev_addr(pipeline->fs.varyings.attribs);
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draw->vs.varyings = panvk_priv_mem_dev_addr(pipeline->link.vs.attribs);
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draw->fs.varyings = panvk_priv_mem_dev_addr(pipeline->link.fs.attribs);
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}
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static void
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@ -126,6 +126,13 @@ struct panvk_shader {
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struct panvk_priv_mem rsd;
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};
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struct panvk_shader_link {
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struct {
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struct panvk_priv_mem attribs;
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} vs, fs;
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unsigned buf_strides[PANVK_VARY_BUF_MAX];
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};
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static inline mali_ptr
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panvk_shader_get_dev_addr(const struct panvk_shader *shader)
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{
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@ -140,6 +147,19 @@ void panvk_per_arch(shader_destroy)(struct panvk_device *dev,
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struct panvk_shader *shader,
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const VkAllocationCallbacks *alloc);
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void panvk_per_arch(link_shaders)(struct panvk_pool *desc_pool,
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struct panvk_shader *vs,
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struct panvk_shader *fs,
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struct panvk_shader_link *link);
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static inline void
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panvk_shader_link_cleanup(struct panvk_pool *desc_pool,
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struct panvk_shader_link *link)
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{
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panvk_pool_free_mem(desc_pool, link->vs.attribs);
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panvk_pool_free_mem(desc_pool, link->fs.attribs);
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}
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bool panvk_per_arch(nir_lower_descriptors)(
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nir_shader *nir, struct panvk_device *dev,
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const struct vk_pipeline_layout *layout, struct panvk_shader *shader);
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@ -413,3 +413,204 @@ panvk_per_arch(shader_destroy)(struct panvk_device *dev,
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free((void *)shader->bin_ptr);
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vk_free2(&dev->vk.alloc, alloc, shader);
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}
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static mali_pixel_format
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get_varying_format(gl_shader_stage stage, gl_varying_slot loc,
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enum pipe_format pfmt)
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{
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switch (loc) {
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case VARYING_SLOT_PNTC:
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case VARYING_SLOT_PSIZ:
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#if PAN_ARCH <= 6
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return (MALI_R16F << 12) | panfrost_get_default_swizzle(1);
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#else
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return (MALI_R16F << 12) | MALI_RGB_COMPONENT_ORDER_R000;
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#endif
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case VARYING_SLOT_POS:
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#if PAN_ARCH <= 6
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return (MALI_SNAP_4 << 12) | panfrost_get_default_swizzle(4);
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#else
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return (MALI_SNAP_4 << 12) | MALI_RGB_COMPONENT_ORDER_RGBA;
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#endif
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default:
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assert(pfmt != PIPE_FORMAT_NONE);
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return GENX(panfrost_format_from_pipe_format)(pfmt)->hw;
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}
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}
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struct varyings_info {
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enum pipe_format fmts[VARYING_SLOT_MAX];
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BITSET_DECLARE(active, VARYING_SLOT_MAX);
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};
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static void
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collect_varyings_info(const struct pan_shader_varying *varyings,
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unsigned varying_count, struct varyings_info *info)
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{
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for (unsigned i = 0; i < varying_count; i++) {
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gl_varying_slot loc = varyings[i].location;
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if (varyings[i].format == PIPE_FORMAT_NONE)
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continue;
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info->fmts[loc] = varyings[i].format;
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BITSET_SET(info->active, loc);
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}
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}
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static inline enum panvk_varying_buf_id
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varying_buf_id(gl_varying_slot loc)
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{
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switch (loc) {
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case VARYING_SLOT_POS:
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return PANVK_VARY_BUF_POSITION;
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case VARYING_SLOT_PSIZ:
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return PANVK_VARY_BUF_PSIZ;
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default:
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return PANVK_VARY_BUF_GENERAL;
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}
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}
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static mali_pixel_format
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varying_format(gl_varying_slot loc, enum pipe_format pfmt)
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{
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switch (loc) {
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case VARYING_SLOT_PNTC:
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case VARYING_SLOT_PSIZ:
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#if PAN_ARCH <= 6
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return (MALI_R16F << 12) | panfrost_get_default_swizzle(1);
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#else
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return (MALI_R16F << 12) | MALI_RGB_COMPONENT_ORDER_R000;
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#endif
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case VARYING_SLOT_POS:
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#if PAN_ARCH <= 6
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return (MALI_SNAP_4 << 12) | panfrost_get_default_swizzle(4);
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#else
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return (MALI_SNAP_4 << 12) | MALI_RGB_COMPONENT_ORDER_RGBA;
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#endif
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default:
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return GENX(panfrost_format_from_pipe_format)(pfmt)->hw;
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}
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}
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static struct panvk_priv_mem
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emit_varying_attrs(struct panvk_pool *desc_pool,
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const struct pan_shader_varying *varyings,
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unsigned varying_count, const struct varyings_info *info,
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unsigned *buf_offsets)
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{
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unsigned attr_count = BITSET_COUNT(info->active);
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struct panvk_priv_mem mem =
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panvk_pool_alloc_desc_array(desc_pool, attr_count, ATTRIBUTE);
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struct mali_attribute_packed *attrs = panvk_priv_mem_host_addr(mem);
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unsigned attr_idx = 0;
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for (unsigned i = 0; i < varying_count; i++) {
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pan_pack(&attrs[attr_idx++], ATTRIBUTE, cfg) {
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gl_varying_slot loc = varyings[i].location;
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||||
enum pipe_format pfmt = varyings[i].format != PIPE_FORMAT_NONE
|
||||
? info->fmts[loc]
|
||||
: PIPE_FORMAT_NONE;
|
||||
|
||||
if (pfmt == PIPE_FORMAT_NONE) {
|
||||
#if PAN_ARCH >= 7
|
||||
cfg.format = (MALI_CONSTANT << 12) | MALI_RGB_COMPONENT_ORDER_0000;
|
||||
#else
|
||||
cfg.format = (MALI_CONSTANT << 12) | PAN_V6_SWIZZLE(0, 0, 0, 0);
|
||||
#endif
|
||||
} else {
|
||||
cfg.buffer_index = varying_buf_id(loc);
|
||||
cfg.offset = buf_offsets[loc];
|
||||
cfg.format = varying_format(loc, info->fmts[loc]);
|
||||
}
|
||||
cfg.offset_enable = false;
|
||||
}
|
||||
}
|
||||
|
||||
return mem;
|
||||
}
|
||||
|
||||
void
|
||||
panvk_per_arch(link_shaders)(struct panvk_pool *desc_pool,
|
||||
struct panvk_shader *vs, struct panvk_shader *fs,
|
||||
struct panvk_shader_link *link)
|
||||
{
|
||||
BITSET_DECLARE(active_attrs, VARYING_SLOT_MAX) = {0};
|
||||
unsigned buf_strides[PANVK_VARY_BUF_MAX] = {0};
|
||||
unsigned buf_offsets[VARYING_SLOT_MAX] = {0};
|
||||
struct varyings_info out_vars = {0};
|
||||
struct varyings_info in_vars = {0};
|
||||
unsigned loc;
|
||||
|
||||
assert(vs);
|
||||
assert(vs->info.stage == MESA_SHADER_VERTEX);
|
||||
|
||||
collect_varyings_info(vs->info.varyings.output,
|
||||
vs->info.varyings.output_count, &out_vars);
|
||||
|
||||
if (fs) {
|
||||
assert(fs->info.stage == MESA_SHADER_FRAGMENT);
|
||||
collect_varyings_info(fs->info.varyings.input,
|
||||
fs->info.varyings.input_count, &in_vars);
|
||||
}
|
||||
|
||||
BITSET_OR(active_attrs, in_vars.active, out_vars.active);
|
||||
|
||||
/* Handle the position and point size buffers explicitly, as they are
|
||||
* passed through separate buffer pointers to the tiler job.
|
||||
*/
|
||||
if (BITSET_TEST(out_vars.active, VARYING_SLOT_POS)) {
|
||||
buf_strides[PANVK_VARY_BUF_POSITION] = sizeof(float) * 4;
|
||||
BITSET_CLEAR(active_attrs, VARYING_SLOT_POS);
|
||||
}
|
||||
|
||||
if (BITSET_TEST(out_vars.active, VARYING_SLOT_PSIZ)) {
|
||||
buf_strides[PANVK_VARY_BUF_PSIZ] = sizeof(uint16_t);
|
||||
BITSET_CLEAR(active_attrs, VARYING_SLOT_PSIZ);
|
||||
}
|
||||
|
||||
BITSET_FOREACH_SET(loc, active_attrs, VARYING_SLOT_MAX) {
|
||||
/* We expect the VS to write to all inputs read by the FS, and the
|
||||
* FS to read all inputs written by the VS. If that's not the
|
||||
* case, we keep PIPE_FORMAT_NONE to reflect the fact we should use a
|
||||
* sink attribute (writes are discarded, reads return zeros).
|
||||
*/
|
||||
if (in_vars.fmts[loc] == PIPE_FORMAT_NONE ||
|
||||
out_vars.fmts[loc] == PIPE_FORMAT_NONE) {
|
||||
in_vars.fmts[loc] = PIPE_FORMAT_NONE;
|
||||
out_vars.fmts[loc] = PIPE_FORMAT_NONE;
|
||||
continue;
|
||||
}
|
||||
|
||||
unsigned out_size = util_format_get_blocksize(out_vars.fmts[loc]);
|
||||
unsigned buf_idx = varying_buf_id(loc);
|
||||
|
||||
/* Always trust the VS input format, so we can:
|
||||
* - discard components that are never read
|
||||
* - use float types for interpolated fragment shader inputs
|
||||
* - use fp16 for floats with mediump
|
||||
* - make sure components that are not written by the FS are set to zero
|
||||
*/
|
||||
out_vars.fmts[loc] = in_vars.fmts[loc];
|
||||
|
||||
/* Special buffers are handled explicitly before this loop, everything
|
||||
* else should be laid out in the general varying buffer.
|
||||
*/
|
||||
assert(buf_idx == PANVK_VARY_BUF_GENERAL);
|
||||
|
||||
/* Keep things aligned a 32-bit component. */
|
||||
buf_offsets[loc] = buf_strides[buf_idx];
|
||||
buf_strides[buf_idx] += ALIGN_POT(out_size, 4);
|
||||
}
|
||||
|
||||
link->vs.attribs = emit_varying_attrs(desc_pool, vs->info.varyings.output,
|
||||
vs->info.varyings.output_count,
|
||||
&out_vars, buf_offsets);
|
||||
|
||||
if (fs)
|
||||
link->fs.attribs = emit_varying_attrs(desc_pool, fs->info.varyings.input,
|
||||
fs->info.varyings.input_count,
|
||||
&in_vars, buf_offsets);
|
||||
|
||||
memcpy(link->buf_strides, buf_strides, sizeof(link->buf_strides));
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue