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radeonsi: Remove tess bits from VS state.

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These parts are not used anymore, therefore we no longer need to
change the VS state when tessellation states change.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28425>
This commit is contained in:
Timur Kristóf 2024-03-30 00:14:42 +01:00
parent b82614e06b
commit 04dea4aef2
4 changed files with 5 additions and 26 deletions
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2
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -1205,7 +1205,7 @@ struct si_context {
int last_primitive_restart_en;
unsigned last_restart_index;
unsigned last_prim;
unsigned current_vs_state; /* all VS bits including LS bits */
unsigned current_vs_state; /* all VS bits */
unsigned current_gs_state; /* only GS and NGG bits */
unsigned last_vs_state;
unsigned last_gs_state;

15
src/gallium/drivers/radeonsi/si_shader.h
View file

@ -235,21 +235,6 @@ enum
#define VS_STATE_INDEXED__SHIFT 1
#define VS_STATE_INDEXED__MASK 0x1 /* Shared by VS and GS */
/* These fields are only set in current_vs_state in si_context, and they are accessible
* in the shader via vs_state_bits in LS/HS.
*/
/* bit gap */
/* TCS output patch0 offset for per-patch outputs / 4
* - 64 outputs are implied by SI_UNIQUE_SLOT_* values.
* - max = 32(CPs) * 64(outputs) * 16(vec4) * 64(num_patches) * 2(inputs + outputs) / 4
* = 1M, clamped to 32K(LDS limit) / 4 = 8K
* - only used by si_llvm_tcs_build_end, it can be removed after NIR lowering replaces it
*/
#define VS_STATE_TCS_OUT_PATCH0_OFFSET__SHIFT 10
#define VS_STATE_TCS_OUT_PATCH0_OFFSET__MASK 0x3fff
#define VS_STATE_LS_OUT_VERTEX_SIZE__SHIFT 24
#define VS_STATE_LS_OUT_VERTEX_SIZE__MASK 0xff /* max 32 * 4 + 1 (to reduce LDS bank conflicts) */
/* These fields are only set in current_gs_state in si_context, and they are accessible
* in the shader via vs_state_bits in legacy GS, the GS copy shader, and any NGG shader.
*/

10
src/gallium/drivers/radeonsi/si_state_draw.cpp
View file

@ -945,16 +945,14 @@ static void si_emit_vs_state(struct si_context *sctx, unsigned index_size)
return;
}
unsigned vs_state = sctx->current_vs_state; /* all VS bits including LS bits */
unsigned vs_state = sctx->current_vs_state; /* all VS bits */
unsigned gs_state = sctx->current_gs_state; /* only GS and NGG bits; VS bits will be copied here */
if (sctx->shader.vs.cso->info.uses_base_vertex && index_size)
vs_state |= ENCODE_FIELD(VS_STATE_INDEXED, 1);
/* Copy all state bits from vs_state to gs_state except the LS bits. */
gs_state |= vs_state &
CLEAR_FIELD(VS_STATE_TCS_OUT_PATCH0_OFFSET) &
CLEAR_FIELD(VS_STATE_LS_OUT_VERTEX_SIZE);
/* Copy all state bits from vs_state to gs_state. */
gs_state |= vs_state;
if (vs_state != sctx->last_vs_state ||
((HAS_GS || NGG) && gs_state != sctx->last_gs_state)) {
@ -1989,7 +1987,7 @@ static void si_draw(struct pipe_context *ctx,
if (u_trace_perfetto_active(&sctx->ds.trace_context))
trace_si_begin_draw(&sctx->trace);
unsigned instance_count = info->instance_count;
/* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is

4
src/gallium/drivers/radeonsi/si_state_shaders.cpp
View file

@ -4623,10 +4623,6 @@ void si_update_tess_io_layout_state(struct si_context *sctx)
lds_size = align(lds_size, 256) / 256;
}
/* Set SI_SGPR_VS_STATE_BITS. */
SET_FIELD(sctx->current_vs_state, VS_STATE_LS_OUT_VERTEX_SIZE, input_vertex_size / 4);
SET_FIELD(sctx->current_vs_state, VS_STATE_TCS_OUT_PATCH0_OFFSET, perpatch_output_offset / 4);
/* We should be able to support in-shader LDS use with LLVM >= 9
* by just adding the lds_sizes together, but it has never
* been tested. */