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amd: import libdrm_amdgpu ioctl wrappers

Browse source 
This imports 35 libdrm_amdgpu functions into Mesa.

The following 15 functions are still in use:
   amdgpu_bo_alloc
   amdgpu_bo_cpu_map
   amdgpu_bo_cpu_unmap
   amdgpu_bo_export
   amdgpu_bo_free
   amdgpu_bo_import
   amdgpu_create_bo_from_user_mem
   amdgpu_device_deinitialize
   amdgpu_device_get_fd
   amdgpu_device_initialize
   amdgpu_get_marketing_name
   amdgpu_query_sw_info
   amdgpu_va_get_start_addr
   amdgpu_va_range_alloc
   amdgpu_va_range_free

We can't import them because they make sure that we only use 1 VMID
per process shared by all APIs. (except the marketing name)

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32067>
This commit is contained in:
Marek Olšák 2024-11-08 21:46:47 -05:00
parent 65b73e6d87
commit 049641ca54
14 changed files with 939 additions and 217 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
src/amd/common/.clang-format Normal file
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@ -0,0 +1,11 @@
BasedOnStyle: InheritParentConfig
# clang-format is not enabled by default for this subdirectory. This file
# is only here for reference. Uncommenting this will enable it for git:
#DisableFormat: false
AlignOperands: Align
AlignTrailingComments: true
AlwaysBreakAfterReturnType: None
ColumnLimit: 100
SpaceAfterTemplateKeyword: false

114
src/amd/common/ac_gpu_info.c
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@ -9,6 +9,7 @@
#include "ac_debug.h"
#include "ac_surface.h"
#include "ac_fake_hw_db.h"
#include "ac_linux_drm.h"
#include "addrlib/src/amdgpu_asic_addr.h"
#include "sid.h"
@ -231,14 +232,6 @@ struct amdgpu_bo_alloc_request {
uint32_t preferred_heap;
uint64_t flags;
};
struct amdgpu_gds_resource_info {
uint32_t gds_gfx_partition_size;
uint32_t gds_total_size;
};
struct amdgpu_buffer_size_alignments {
uint64_t size_local;
uint64_t size_remote;
};
struct amdgpu_heap_info {
uint64_t heap_size;
};
@ -286,59 +279,11 @@ static int amdgpu_bo_free(amdgpu_bo_handle buf_handle)
{
return -EINVAL;
}
static int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
struct amdgpu_buffer_size_alignments
*info)
{
return -EINVAL;
}
static int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
unsigned ip_instance, unsigned index,
uint32_t *version, uint32_t *feature)
{
return -EINVAL;
}
static int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
unsigned ip_instance,
struct drm_amdgpu_info_hw_ip *info)
{
return -EINVAL;
}
static int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type,
uint32_t *count)
{
return -EINVAL;
}
static int amdgpu_query_heap_info(amdgpu_device_handle dev, uint32_t heap,
uint32_t flags, struct amdgpu_heap_info *info)
{
return -EINVAL;
}
static int amdgpu_query_gpu_info(amdgpu_device_handle dev,
struct amdgpu_gpu_info *info)
{
return -EINVAL;
}
static int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
unsigned size, void *value)
{
return -EINVAL;
}
static int amdgpu_query_sw_info(amdgpu_device_handle dev, enum amdgpu_sw_info info,
void *value)
{
return -EINVAL;
}
static int amdgpu_query_gds_info(amdgpu_device_handle dev,
struct amdgpu_gds_resource_info *gds_info)
{
return -EINVAL;
}
static int amdgpu_query_video_caps_info(amdgpu_device_handle dev, unsigned cap_type,
unsigned size, void *value)
{
return -EINVAL;
}
static const char *amdgpu_get_marketing_name(amdgpu_device_handle dev)
{
return NULL;
@ -609,7 +554,6 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
{
struct amdgpu_gpu_info amdinfo;
struct drm_amdgpu_info_device device_info = {0};
struct amdgpu_buffer_size_alignments alignment_info = {0};
uint32_t vidip_fw_version = 0, vidip_fw_feature = 0;
uint32_t num_instances = 0;
int r, i, j;
@ -651,28 +595,22 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
}
/* Query hardware and driver information. */
r = amdgpu_query_gpu_info(dev, &amdinfo);
r = ac_drm_query_gpu_info(fd, &amdinfo);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
fprintf(stderr, "amdgpu: ac_drm_query_gpu_info failed.\n");
return false;
}
r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(device_info), &device_info);
r = ac_drm_query_info(fd, AMDGPU_INFO_DEV_INFO, sizeof(device_info), &device_info);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_info(dev_info) failed.\n");
return false;
}
r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
fprintf(stderr, "amdgpu: ac_drm_query_info(dev_info) failed.\n");
return false;
}
for (unsigned ip_type = 0; ip_type < AMD_NUM_IP_TYPES; ip_type++) {
struct drm_amdgpu_info_hw_ip ip_info = {0};
r = amdgpu_query_hw_ip_info(dev, ip_type, 0, &ip_info);
r = ac_drm_query_hw_ip_info(fd, ip_type, 0, &ip_info);
if (r || !ip_info.available_rings)
continue;
@ -701,7 +639,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->ip[ip_type].num_queues = util_bitcount(ip_info.available_rings);
/* query ip count */
r = amdgpu_query_hw_ip_count(dev, ip_type, &num_instances);
r = ac_drm_query_hw_ip_count(fd, ip_type, &num_instances);
if (!r)
info->ip[ip_type].num_instances = num_instances;
@ -732,31 +670,31 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
return false;
}
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0, &info->me_fw_version,
r = ac_drm_query_firmware_version(fd, AMDGPU_INFO_FW_GFX_ME, 0, 0, &info->me_fw_version,
&info->me_fw_feature);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
fprintf(stderr, "amdgpu: ac_drm_query_firmware_version(me) failed.\n");
return false;
}
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_MEC, 0, 0, &info->mec_fw_version,
r = ac_drm_query_firmware_version(fd, AMDGPU_INFO_FW_GFX_MEC, 0, 0, &info->mec_fw_version,
&info->mec_fw_feature);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(mec) failed.\n");
fprintf(stderr, "amdgpu: ac_drm_query_firmware_version(mec) failed.\n");
return false;
}
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0, &info->pfp_fw_version,
r = ac_drm_query_firmware_version(fd, AMDGPU_INFO_FW_GFX_PFP, 0, 0, &info->pfp_fw_version,
&info->pfp_fw_feature);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
fprintf(stderr, "amdgpu: ac_drm_query_firmware_version(pfp) failed.\n");
return false;
}
if (info->ip[AMD_IP_VCN_DEC].num_queues || info->ip[AMD_IP_VCN_UNIFIED].num_queues) {
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCN, 0, 0, &vidip_fw_version, &vidip_fw_feature);
r = ac_drm_query_firmware_version(fd, AMDGPU_INFO_FW_VCN, 0, 0, &vidip_fw_version, &vidip_fw_feature);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vcn) failed.\n");
fprintf(stderr, "amdgpu: ac_drm_query_firmware_version(vcn) failed.\n");
return false;
} else {
info->vcn_dec_version = (vidip_fw_version & 0x0F000000) >> 24;
@ -765,18 +703,18 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
}
} else {
if (info->ip[AMD_IP_VCE].num_queues) {
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0, &vidip_fw_version, &vidip_fw_feature);
r = ac_drm_query_firmware_version(fd, AMDGPU_INFO_FW_VCE, 0, 0, &vidip_fw_version, &vidip_fw_feature);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
fprintf(stderr, "amdgpu: ac_drm_query_firmware_version(vce) failed.\n");
return false;
} else
info->vce_fw_version = vidip_fw_version;
}
if (info->ip[AMD_IP_UVD].num_queues) {
r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0, &vidip_fw_version, &vidip_fw_feature);
r = ac_drm_query_firmware_version(fd, AMDGPU_INFO_FW_UVD, 0, 0, &vidip_fw_version, &vidip_fw_feature);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
fprintf(stderr, "amdgpu: ac_drm_query_firmware_version(uvd) failed.\n");
return false;
} else
info->uvd_fw_version = vidip_fw_version;
@ -791,9 +729,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
struct drm_amdgpu_memory_info meminfo = {0};
r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo), &meminfo);
r = ac_drm_query_info(fd, AMDGPU_INFO_MEMORY, sizeof(meminfo), &meminfo);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_query_info(memory) failed.\n");
fprintf(stderr, "amdgpu: ac_drm_query_info(memory) failed.\n");
return false;
}
@ -803,9 +741,9 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
info->vram_vis_size_kb = DIV_ROUND_UP(meminfo.cpu_accessible_vram.total_heap_size, 1024);
if (info->drm_minor >= 41) {
amdgpu_query_video_caps_info(dev, AMDGPU_INFO_VIDEO_CAPS_DECODE,
ac_drm_query_video_caps_info(fd, AMDGPU_INFO_VIDEO_CAPS_DECODE,
sizeof(info->dec_caps), &(info->dec_caps));
amdgpu_query_video_caps_info(dev, AMDGPU_INFO_VIDEO_CAPS_ENCODE,
ac_drm_query_video_caps_info(fd, AMDGPU_INFO_VIDEO_CAPS_ENCODE,
sizeof(info->enc_caps), &(info->enc_caps));
}
@ -1459,8 +1397,8 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
memcpy(info->cik_macrotile_mode_array, amdinfo.gb_macro_tile_mode,
sizeof(amdinfo.gb_macro_tile_mode));
info->pte_fragment_size = alignment_info.size_local;
info->gart_page_size = alignment_info.size_remote;
info->pte_fragment_size = device_info.pte_fragment_size;
info->gart_page_size = device_info.gart_page_size;
info->gfx_ib_pad_with_type2 = info->gfx_level == GFX6;
/* CDNA starting with GFX940 shouldn't use CP DMA. */
@ -1659,7 +1597,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
* It can be calculated according to the kernel source code as:
* (ring->max_dw - emit_frame_size) / emit_ib_size
*/
r = amdgpu_query_info(dev, AMDGPU_INFO_MAX_IBS,
r = ac_drm_query_info(fd, AMDGPU_INFO_MAX_IBS,
sizeof(info->max_submitted_ibs), info->max_submitted_ibs);
if (r) {
/* When the number of IBs can't be queried from the kernel, we choose a

644
src/amd/common/ac_linux_drm.c Normal file
View file

@ -0,0 +1,644 @@
/*
* Copyright 2024 Advanced Micro Devices, Inc.
* SPDX-License-Identifier: MIT
*/
#include "ac_linux_drm.h"
#include "util/u_math.h"
#include <errno.h>
#include <stdlib.h>
#include <time.h>
#include <unistd.h>
#include <xf86drm.h>
int ac_drm_bo_set_metadata(int device_fd, uint32_t bo_handle, struct amdgpu_bo_metadata *info)
{
struct drm_amdgpu_gem_metadata args = {};
args.handle = bo_handle;
args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA;
args.data.flags = info->flags;
args.data.tiling_info = info->tiling_info;
if (info->size_metadata > sizeof(args.data.data))
return -EINVAL;
if (info->size_metadata) {
args.data.data_size_bytes = info->size_metadata;
memcpy(args.data.data, info->umd_metadata, info->size_metadata);
}
return drmCommandWriteRead(device_fd, DRM_AMDGPU_GEM_METADATA, &args, sizeof(args));
}
int ac_drm_bo_query_info(int device_fd, uint32_t bo_handle, struct amdgpu_bo_info *info)
{
struct drm_amdgpu_gem_metadata metadata = {};
struct drm_amdgpu_gem_create_in bo_info = {};
struct drm_amdgpu_gem_op gem_op = {};
int r;
/* Validate the BO passed in */
if (!bo_handle)
return -EINVAL;
/* Query metadata. */
metadata.handle = bo_handle;
metadata.op = AMDGPU_GEM_METADATA_OP_GET_METADATA;
r = drmCommandWriteRead(device_fd, DRM_AMDGPU_GEM_METADATA, &metadata, sizeof(metadata));
if (r)
return r;
if (metadata.data.data_size_bytes > sizeof(info->metadata.umd_metadata))
return -EINVAL;
/* Query buffer info. */
gem_op.handle = bo_handle;
gem_op.op = AMDGPU_GEM_OP_GET_GEM_CREATE_INFO;
gem_op.value = (uintptr_t)&bo_info;
r = drmCommandWriteRead(device_fd, DRM_AMDGPU_GEM_OP, &gem_op, sizeof(gem_op));
if (r)
return r;
memset(info, 0, sizeof(*info));
info->alloc_size = bo_info.bo_size;
info->phys_alignment = bo_info.alignment;
info->preferred_heap = bo_info.domains;
info->alloc_flags = bo_info.domain_flags;
info->metadata.flags = metadata.data.flags;
info->metadata.tiling_info = metadata.data.tiling_info;
info->metadata.size_metadata = metadata.data.data_size_bytes;
if (metadata.data.data_size_bytes > 0)
memcpy(info->metadata.umd_metadata, metadata.data.data, metadata.data.data_size_bytes);
return 0;
}
static uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout)
{
int r;
if (timeout != AMDGPU_TIMEOUT_INFINITE) {
struct timespec current;
uint64_t current_ns;
r = clock_gettime(CLOCK_MONOTONIC, &current);
if (r) {
fprintf(stderr, "clock_gettime() returned error (%d)!", errno);
return AMDGPU_TIMEOUT_INFINITE;
}
current_ns = ((uint64_t)current.tv_sec) * 1000000000ull;
current_ns += current.tv_nsec;
timeout += current_ns;
if (timeout < current_ns)
timeout = AMDGPU_TIMEOUT_INFINITE;
}
return timeout;
}
int ac_drm_bo_wait_for_idle(int device_fd, uint32_t bo_handle, uint64_t timeout_ns, bool *busy)
{
union drm_amdgpu_gem_wait_idle args;
int r;
memset(&args, 0, sizeof(args));
args.in.handle = bo_handle;
args.in.timeout = amdgpu_cs_calculate_timeout(timeout_ns);
r = drmCommandWriteRead(device_fd, DRM_AMDGPU_GEM_WAIT_IDLE, &args, sizeof(args));
if (r == 0) {
*busy = args.out.status;
return 0;
} else {
fprintf(stderr, "amdgpu: GEM_WAIT_IDLE failed with %i\n", r);
return r;
}
}
int ac_drm_bo_va_op(int device_fd, uint32_t bo_handle, uint64_t offset, uint64_t size,
uint64_t addr, uint64_t flags, uint32_t ops)
{
size = ALIGN(size, getpagesize());
return ac_drm_bo_va_op_raw(
device_fd, bo_handle, offset, size, addr,
AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE, ops);
}
int ac_drm_bo_va_op_raw(int device_fd, uint32_t bo_handle, uint64_t offset, uint64_t size,
uint64_t addr, uint64_t flags, uint32_t ops)
{
struct drm_amdgpu_gem_va va;
int r;
if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP && ops != AMDGPU_VA_OP_REPLACE &&
ops != AMDGPU_VA_OP_CLEAR)
return -EINVAL;
memset(&va, 0, sizeof(va));
va.handle = bo_handle;
va.operation = ops;
va.flags = flags;
va.va_address = addr;
va.offset_in_bo = offset;
va.map_size = size;
r = drmCommandWriteRead(device_fd, DRM_AMDGPU_GEM_VA, &va, sizeof(va));
return r;
}
int ac_drm_cs_ctx_create2(int device_fd, uint32_t priority, uint32_t *ctx_handle)
{
union drm_amdgpu_ctx args;
int r;
char *override_priority;
override_priority = getenv("AMD_PRIORITY");
if (override_priority) {
/* The priority is a signed integer. The variable type is
* wrong. If parsing fails, priority is unchanged.
*/
if (sscanf(override_priority, "%i", &priority) == 1) {
printf("amdgpu: context priority changed to %i\n", priority);
}
}
/* Create the context */
memset(&args, 0, sizeof(args));
args.in.op = AMDGPU_CTX_OP_ALLOC_CTX;
args.in.priority = priority;
r = drmCommandWriteRead(device_fd, DRM_AMDGPU_CTX, &args, sizeof(args));
if (r)
return r;
*ctx_handle = args.out.alloc.ctx_id;
return 0;
}
int ac_drm_cs_ctx_free(int device_fd, uint32_t ctx_handle)
{
union drm_amdgpu_ctx args;
/* now deal with kernel side */
memset(&args, 0, sizeof(args));
args.in.op = AMDGPU_CTX_OP_FREE_CTX;
args.in.ctx_id = ctx_handle;
return drmCommandWriteRead(device_fd, DRM_AMDGPU_CTX, &args, sizeof(args));
}
int ac_drm_cs_ctx_stable_pstate(int device_fd, uint32_t ctx_handle, uint32_t op, uint32_t flags,
uint32_t *out_flags)
{
union drm_amdgpu_ctx args;
int r;
if (!ctx_handle)
return -EINVAL;
memset(&args, 0, sizeof(args));
args.in.op = op;
args.in.ctx_id = ctx_handle;
args.in.flags = flags;
r = drmCommandWriteRead(device_fd, DRM_AMDGPU_CTX, &args, sizeof(args));
if (!r && out_flags)
*out_flags = args.out.pstate.flags;
return r;
}
int ac_drm_cs_query_reset_state2(int device_fd, uint32_t ctx_handle, uint64_t *flags)
{
union drm_amdgpu_ctx args;
int r;
if (!ctx_handle)
return -EINVAL;
memset(&args, 0, sizeof(args));
args.in.op = AMDGPU_CTX_OP_QUERY_STATE2;
args.in.ctx_id = ctx_handle;
r = drmCommandWriteRead(device_fd, DRM_AMDGPU_CTX, &args, sizeof(args));
if (!r)
*flags = args.out.state.flags;
return r;
}
static int amdgpu_ioctl_wait_cs(int device_fd, uint32_t ctx_handle, unsigned ip,
unsigned ip_instance, uint32_t ring, uint64_t handle,
uint64_t timeout_ns, uint64_t flags, bool *busy)
{
union drm_amdgpu_wait_cs args;
int r;
memset(&args, 0, sizeof(args));
args.in.handle = handle;
args.in.ip_type = ip;
args.in.ip_instance = ip_instance;
args.in.ring = ring;
args.in.ctx_id = ctx_handle;
if (flags & AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE)
args.in.timeout = timeout_ns;
else
args.in.timeout = amdgpu_cs_calculate_timeout(timeout_ns);
r = drmIoctl(device_fd, DRM_IOCTL_AMDGPU_WAIT_CS, &args);
if (r)
return -errno;
*busy = args.out.status;
return 0;
}
int ac_drm_cs_query_fence_status(int device_fd, uint32_t ctx_handle, uint32_t ip_type,
uint32_t ip_instance, uint32_t ring, uint64_t fence_seq_no,
uint64_t timeout_ns, uint64_t flags, uint32_t *expired)
{
bool busy = true;
int r;
if (!fence_seq_no) {
*expired = true;
return 0;
}
*expired = false;
r = amdgpu_ioctl_wait_cs(device_fd, ctx_handle, ip_type, ip_instance, ring, fence_seq_no,
timeout_ns, flags, &busy);
if (!r && !busy)
*expired = true;
return r;
}
int ac_drm_cs_create_syncobj2(int device_fd, uint32_t flags, uint32_t *handle)
{
return drmSyncobjCreate(device_fd, flags, handle);
}
int ac_drm_cs_create_syncobj(int device_fd, uint32_t *handle)
{
return drmSyncobjCreate(device_fd, 0, handle);
}
int ac_drm_cs_destroy_syncobj(int device_fd, uint32_t handle)
{
return drmSyncobjDestroy(device_fd, handle);
}
int ac_drm_cs_syncobj_wait(int device_fd, uint32_t *handles, unsigned num_handles,
int64_t timeout_nsec, unsigned flags, uint32_t *first_signaled)
{
return drmSyncobjWait(device_fd, handles, num_handles, timeout_nsec, flags, first_signaled);
}
int ac_drm_cs_syncobj_query2(int device_fd, uint32_t *handles, uint64_t *points,
unsigned num_handles, uint32_t flags)
{
return drmSyncobjQuery2(device_fd, handles, points, num_handles, flags);
}
int ac_drm_cs_import_syncobj(int device_fd, int shared_fd, uint32_t *handle)
{
return drmSyncobjFDToHandle(device_fd, shared_fd, handle);
}
int ac_drm_cs_syncobj_export_sync_file(int device_fd, uint32_t syncobj, int *sync_file_fd)
{
return drmSyncobjExportSyncFile(device_fd, syncobj, sync_file_fd);
}
int ac_drm_cs_syncobj_import_sync_file(int device_fd, uint32_t syncobj, int sync_file_fd)
{
return drmSyncobjImportSyncFile(device_fd, syncobj, sync_file_fd);
}
int ac_drm_cs_syncobj_export_sync_file2(int device_fd, uint32_t syncobj, uint64_t point,
uint32_t flags, int *sync_file_fd)
{
uint32_t binary_handle;
int ret;
if (!point)
return drmSyncobjExportSyncFile(device_fd, syncobj, sync_file_fd);
ret = drmSyncobjCreate(device_fd, 0, &binary_handle);
if (ret)
return ret;
ret = drmSyncobjTransfer(device_fd, binary_handle, 0, syncobj, point, flags);
if (ret)
goto out;
ret = drmSyncobjExportSyncFile(device_fd, binary_handle, sync_file_fd);
out:
drmSyncobjDestroy(device_fd, binary_handle);
return ret;
}
int ac_drm_cs_syncobj_transfer(int device_fd, uint32_t dst_handle, uint64_t dst_point,
uint32_t src_handle, uint64_t src_point, uint32_t flags)
{
return drmSyncobjTransfer(device_fd, dst_handle, dst_point, src_handle, src_point, flags);
}
int ac_drm_cs_submit_raw2(int device_fd, uint32_t ctx_handle, uint32_t bo_list_handle,
int num_chunks, struct drm_amdgpu_cs_chunk *chunks, uint64_t *seq_no)
{
union drm_amdgpu_cs cs;
uint64_t *chunk_array;
int i, r;
memset(&cs, 0, sizeof(cs));
chunk_array = alloca(sizeof(uint64_t) * num_chunks);
for (i = 0; i < num_chunks; i++)
chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
cs.in.ctx_id = ctx_handle;
cs.in.bo_list_handle = bo_list_handle;
cs.in.num_chunks = num_chunks;
r = drmCommandWriteRead(device_fd, DRM_AMDGPU_CS, &cs, sizeof(cs));
if (!r && seq_no)
*seq_no = cs.out.handle;
return r;
}
void ac_drm_cs_chunk_fence_info_to_data(uint32_t bo_handle, uint64_t offset,
struct drm_amdgpu_cs_chunk_data *data)
{
data->fence_data.handle = bo_handle;
data->fence_data.offset = offset * sizeof(uint64_t);
}
int ac_drm_query_info(int device_fd, unsigned info_id, unsigned size, void *value)
{
struct drm_amdgpu_info request;
memset(&request, 0, sizeof(request));
request.return_pointer = (uintptr_t)value;
request.return_size = size;
request.query = info_id;
return drmCommandWrite(device_fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info));
}
int ac_drm_read_mm_registers(int device_fd, unsigned dword_offset, unsigned count,
uint32_t instance, uint32_t flags, uint32_t *values)
{
struct drm_amdgpu_info request;
memset(&request, 0, sizeof(request));
request.return_pointer = (uintptr_t)values;
request.return_size = count * sizeof(uint32_t);
request.query = AMDGPU_INFO_READ_MMR_REG;
request.read_mmr_reg.dword_offset = dword_offset;
request.read_mmr_reg.count = count;
request.read_mmr_reg.instance = instance;
request.read_mmr_reg.flags = flags;
return drmCommandWrite(device_fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info));
}
int ac_drm_query_hw_ip_count(int device_fd, unsigned type, uint32_t *count)
{
struct drm_amdgpu_info request;
memset(&request, 0, sizeof(request));
request.return_pointer = (uintptr_t)count;
request.return_size = sizeof(*count);
request.query = AMDGPU_INFO_HW_IP_COUNT;
request.query_hw_ip.type = type;
return drmCommandWrite(device_fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info));
}
int ac_drm_query_hw_ip_info(int device_fd, unsigned type, unsigned ip_instance,
struct drm_amdgpu_info_hw_ip *info)
{
struct drm_amdgpu_info request;
memset(&request, 0, sizeof(request));
request.return_pointer = (uintptr_t)info;
request.return_size = sizeof(*info);
request.query = AMDGPU_INFO_HW_IP_INFO;
request.query_hw_ip.type = type;
request.query_hw_ip.ip_instance = ip_instance;
return drmCommandWrite(device_fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info));
}
int ac_drm_query_firmware_version(int device_fd, unsigned fw_type, unsigned ip_instance,
unsigned index, uint32_t *version, uint32_t *feature)
{
struct drm_amdgpu_info request;
struct drm_amdgpu_info_firmware firmware = {};
int r;
memset(&request, 0, sizeof(request));
request.return_pointer = (uintptr_t)&firmware;
request.return_size = sizeof(firmware);
request.query = AMDGPU_INFO_FW_VERSION;
request.query_fw.fw_type = fw_type;
request.query_fw.ip_instance = ip_instance;
request.query_fw.index = index;
r = drmCommandWrite(device_fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info));
if (r)
return r;
*version = firmware.ver;
*feature = firmware.feature;
return 0;
}
int ac_drm_query_gpu_info(int device_fd, struct amdgpu_gpu_info *info)
{
struct drm_amdgpu_info_device dev_info = {0};
int r, i;
r = ac_drm_query_info(device_fd, AMDGPU_INFO_DEV_INFO, sizeof(dev_info), &dev_info);
if (r)
return r;
memset(info, 0, sizeof(*info));
info->asic_id = dev_info.device_id;
info->chip_rev = dev_info.chip_rev;
info->chip_external_rev = dev_info.external_rev;
info->family_id = dev_info.family;
info->max_engine_clk = dev_info.max_engine_clock;
info->max_memory_clk = dev_info.max_memory_clock;
info->gpu_counter_freq = dev_info.gpu_counter_freq;
info->enabled_rb_pipes_mask = dev_info.enabled_rb_pipes_mask;
info->rb_pipes = dev_info.num_rb_pipes;
info->ids_flags = dev_info.ids_flags;
info->num_hw_gfx_contexts = dev_info.num_hw_gfx_contexts;
info->num_shader_engines = dev_info.num_shader_engines;
info->num_shader_arrays_per_engine = dev_info.num_shader_arrays_per_engine;
info->vram_type = dev_info.vram_type;
info->vram_bit_width = dev_info.vram_bit_width;
info->ce_ram_size = dev_info.ce_ram_size;
info->vce_harvest_config = dev_info.vce_harvest_config;
info->pci_rev_id = dev_info.pci_rev;
if (info->family_id < AMDGPU_FAMILY_AI) {
for (i = 0; i < (int)info->num_shader_engines; i++) {
unsigned instance = (i << AMDGPU_INFO_MMR_SE_INDEX_SHIFT) |
(AMDGPU_INFO_MMR_SH_INDEX_MASK << AMDGPU_INFO_MMR_SH_INDEX_SHIFT);
r = ac_drm_read_mm_registers(device_fd, 0x263d, 1, instance, 0, &info->backend_disable[i]);
if (r)
return r;
/* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
info->backend_disable[i] = (info->backend_disable[i] >> 16) & 0xff;
r =
ac_drm_read_mm_registers(device_fd, 0xa0d4, 1, instance, 0, &info->pa_sc_raster_cfg[i]);
if (r)
return r;
if (info->family_id >= AMDGPU_FAMILY_CI) {
r = ac_drm_read_mm_registers(device_fd, 0xa0d5, 1, instance, 0,
&info->pa_sc_raster_cfg1[i]);
if (r)
return r;
}
}
}
r = ac_drm_read_mm_registers(device_fd, 0x263e, 1, 0xffffffff, 0, &info->gb_addr_cfg);
if (r)
return r;
if (info->family_id < AMDGPU_FAMILY_AI) {
r = ac_drm_read_mm_registers(device_fd, 0x2644, 32, 0xffffffff, 0, info->gb_tile_mode);
if (r)
return r;
if (info->family_id >= AMDGPU_FAMILY_CI) {
r = ac_drm_read_mm_registers(device_fd, 0x2664, 16, 0xffffffff, 0,
info->gb_macro_tile_mode);
if (r)
return r;
}
r = ac_drm_read_mm_registers(device_fd, 0x9d8, 1, 0xffffffff, 0, &info->mc_arb_ramcfg);
if (r)
return r;
}
info->cu_active_number = dev_info.cu_active_number;
info->cu_ao_mask = dev_info.cu_ao_mask;
memcpy(&info->cu_bitmap[0][0], &dev_info.cu_bitmap[0][0], sizeof(info->cu_bitmap));
return 0;
}
int ac_drm_query_heap_info(int device_fd, uint32_t heap, uint32_t flags,
struct amdgpu_heap_info *info)
{
struct drm_amdgpu_info_vram_gtt vram_gtt_info = {};
int r;
r = ac_drm_query_info(device_fd, AMDGPU_INFO_VRAM_GTT, sizeof(vram_gtt_info), &vram_gtt_info);
if (r)
return r;
/* Get heap information */
switch (heap) {
case AMDGPU_GEM_DOMAIN_VRAM:
/* query visible only vram heap */
if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
info->heap_size = vram_gtt_info.vram_cpu_accessible_size;
else /* query total vram heap */
info->heap_size = vram_gtt_info.vram_size;
info->max_allocation = vram_gtt_info.vram_cpu_accessible_size;
if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
r = ac_drm_query_info(device_fd, AMDGPU_INFO_VIS_VRAM_USAGE, sizeof(info->heap_usage),
&info->heap_usage);
else
r = ac_drm_query_info(device_fd, AMDGPU_INFO_VRAM_USAGE, sizeof(info->heap_usage),
&info->heap_usage);
if (r)
return r;
break;
case AMDGPU_GEM_DOMAIN_GTT:
info->heap_size = vram_gtt_info.gtt_size;
info->max_allocation = vram_gtt_info.vram_cpu_accessible_size;
r = ac_drm_query_info(device_fd, AMDGPU_INFO_GTT_USAGE, sizeof(info->heap_usage),
&info->heap_usage);
if (r)
return r;
break;
default:
return -EINVAL;
}
return 0;
}
int ac_drm_query_sensor_info(int device_fd, unsigned sensor_type, unsigned size, void *value)
{
struct drm_amdgpu_info request;
memset(&request, 0, sizeof(request));
request.return_pointer = (uintptr_t)value;
request.return_size = size;
request.query = AMDGPU_INFO_SENSOR;
request.sensor_info.type = sensor_type;
return drmCommandWrite(device_fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info));
}
int ac_drm_query_video_caps_info(int device_fd, unsigned cap_type, unsigned size, void *value)
{
struct drm_amdgpu_info request;
memset(&request, 0, sizeof(request));
request.return_pointer = (uintptr_t)value;
request.return_size = size;
request.query = AMDGPU_INFO_VIDEO_CAPS;
request.sensor_info.type = cap_type;
return drmCommandWrite(device_fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info));
}
int ac_drm_query_gpuvm_fault_info(int device_fd, unsigned size, void *value)
{
struct drm_amdgpu_info request;
memset(&request, 0, sizeof(request));
request.return_pointer = (uintptr_t)value;
request.return_size = size;
request.query = AMDGPU_INFO_GPUVM_FAULT;
return drmCommandWrite(device_fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info));
}
int ac_drm_vm_reserve_vmid(int device_fd, uint32_t flags)
{
union drm_amdgpu_vm vm;
vm.in.op = AMDGPU_VM_OP_RESERVE_VMID;
vm.in.flags = flags;
return drmCommandWriteRead(device_fd, DRM_AMDGPU_VM, &vm, sizeof(vm));
}
int ac_drm_vm_unreserve_vmid(int device_fd, uint32_t flags)
{
union drm_amdgpu_vm vm;
vm.in.op = AMDGPU_VM_OP_UNRESERVE_VMID;
vm.in.flags = flags;
return drmCommandWriteRead(device_fd, DRM_AMDGPU_VM, &vm, sizeof(vm));
}

98
src/amd/common/ac_linux_drm.h Normal file
View file

@ -0,0 +1,98 @@
/*
* Copyright 2024 Advanced Micro Devices, Inc.
* SPDX-License-Identifier: MIT
*/
#ifndef AC_LINUX_DRM_H
#define AC_LINUX_DRM_H
#include <stdbool.h>
#include <stdint.h>
#ifndef _WIN32
#include "drm-uapi/amdgpu_drm.h"
#include "amdgpu.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/* All functions are static inline stubs on Windows. */
#ifdef _WIN32
#define PROC static inline
#define TAIL \
{ \
return -1; \
}
#define TAILV \
{ \
}
#else
#define PROC
#define TAIL
#define TAILV
#endif
PROC int ac_drm_bo_set_metadata(int device_fd, uint32_t bo_handle,
struct amdgpu_bo_metadata *info) TAIL;
PROC int ac_drm_bo_query_info(int device_fd, uint32_t bo_handle, struct amdgpu_bo_info *info) TAIL;
PROC int ac_drm_bo_wait_for_idle(int device_fd, uint32_t bo_handle, uint64_t timeout_ns,
bool *busy) TAIL;
PROC int ac_drm_bo_va_op(int device_fd, uint32_t bo_handle, uint64_t offset, uint64_t size,
uint64_t addr, uint64_t flags, uint32_t ops) TAIL;
PROC int ac_drm_bo_va_op_raw(int device_fd, uint32_t bo_handle, uint64_t offset, uint64_t size,
uint64_t addr, uint64_t flags, uint32_t ops) TAIL;
PROC int ac_drm_cs_ctx_create2(int device_fd, uint32_t priority, uint32_t *ctx_handle) TAIL;
PROC int ac_drm_cs_ctx_free(int device_fd, uint32_t ctx_handle) TAIL;
PROC int ac_drm_cs_ctx_stable_pstate(int device_fd, uint32_t ctx_handle, uint32_t op,
uint32_t flags, uint32_t *out_flags) TAIL;
PROC int ac_drm_cs_query_reset_state2(int device_fd, uint32_t ctx_handle, uint64_t *flags) TAIL;
PROC int ac_drm_cs_query_fence_status(int device_fd, uint32_t ctx_handle, uint32_t ip_type,
uint32_t ip_instance, uint32_t ring, uint64_t fence_seq_no,
uint64_t timeout_ns, uint64_t flags, uint32_t *expired) TAIL;
PROC int ac_drm_cs_create_syncobj2(int device_fd, uint32_t flags, uint32_t *handle) TAIL;
PROC int ac_drm_cs_create_syncobj(int device_fd, uint32_t *handle) TAIL;
PROC int ac_drm_cs_destroy_syncobj(int device_fd, uint32_t handle) TAIL;
PROC int ac_drm_cs_syncobj_wait(int device_fd, uint32_t *handles, unsigned num_handles,
int64_t timeout_nsec, unsigned flags,
uint32_t *first_signaled) TAIL;
PROC int ac_drm_cs_syncobj_query2(int device_fd, uint32_t *handles, uint64_t *points,
unsigned num_handles, uint32_t flags) TAIL;
PROC int ac_drm_cs_import_syncobj(int device_fd, int shared_fd, uint32_t *handle) TAIL;
PROC int ac_drm_cs_syncobj_export_sync_file(int device_fd, uint32_t syncobj,
int *sync_file_fd) TAIL;
PROC int ac_drm_cs_syncobj_import_sync_file(int device_fd, uint32_t syncobj, int sync_file_fd) TAIL;
PROC int ac_drm_cs_syncobj_export_sync_file2(int device_fd, uint32_t syncobj, uint64_t point,
uint32_t flags, int *sync_file_fd) TAIL;
PROC int ac_drm_cs_syncobj_transfer(int device_fd, uint32_t dst_handle, uint64_t dst_point,
uint32_t src_handle, uint64_t src_point, uint32_t flags) TAIL;
PROC int ac_drm_cs_submit_raw2(int device_fd, uint32_t ctx_handle, uint32_t bo_list_handle,
int num_chunks, struct drm_amdgpu_cs_chunk *chunks,
uint64_t *seq_no) TAIL;
PROC void ac_drm_cs_chunk_fence_info_to_data(uint32_t bo_handle, uint64_t offset,
struct drm_amdgpu_cs_chunk_data *data) TAILV;
PROC int ac_drm_query_info(int device_fd, unsigned info_id, unsigned size, void *value) TAIL;
PROC int ac_drm_read_mm_registers(int device_fd, unsigned dword_offset, unsigned count,
uint32_t instance, uint32_t flags, uint32_t *values) TAIL;
PROC int ac_drm_query_hw_ip_count(int device_fd, unsigned type, uint32_t *count) TAIL;
PROC int ac_drm_query_hw_ip_info(int device_fd, unsigned type, unsigned ip_instance,
struct drm_amdgpu_info_hw_ip *info) TAIL;
PROC int ac_drm_query_firmware_version(int device_fd, unsigned fw_type, unsigned ip_instance,
unsigned index, uint32_t *version, uint32_t *feature) TAIL;
PROC int ac_drm_query_gpu_info(int device_fd, struct amdgpu_gpu_info *info) TAIL;
PROC int ac_drm_query_heap_info(int device_fd, uint32_t heap, uint32_t flags,
struct amdgpu_heap_info *info) TAIL;
PROC int ac_drm_query_sensor_info(int device_fd, unsigned sensor_type, unsigned size,
void *value) TAIL;
PROC int ac_drm_query_video_caps_info(int device_fd, unsigned cap_type, unsigned size,
void *value) TAIL;
PROC int ac_drm_query_gpuvm_fault_info(int device_fd, unsigned size, void *value) TAIL;
PROC int ac_drm_vm_reserve_vmid(int device_fd, uint32_t flags) TAIL;
PROC int ac_drm_vm_unreserve_vmid(int device_fd, uint32_t flags) TAIL;
#ifdef __cplusplus
}
#endif
#endif

7
src/amd/common/meson.build
View file

@ -71,6 +71,7 @@ amd_common_files = files(
'ac_descriptors.h',
'ac_formats.c',
'ac_formats.h',
'ac_linux_drm.h',
'ac_shadowed_regs.c',
'ac_shadowed_regs.h',
'ac_spm.c',
@ -112,6 +113,12 @@ amd_common_files = files(
'ac_vcn_enc.c',
)
if not with_platform_windows
amd_common_files += files(
'ac_linux_drm.c',
)
endif
if dep_elf.found()
amd_common_files += files(
'ac_rtld.c',

66
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
View file

@ -21,6 +21,7 @@
#include <xf86drm.h>
#include "drm-uapi/amdgpu_drm.h"
#include <sys/mman.h>
#include "ac_linux_drm.h"
#include "util/os_time.h"
#include "util/u_atomic.h"
@ -30,11 +31,11 @@
static void radv_amdgpu_winsys_bo_destroy(struct radeon_winsys *_ws, struct radeon_winsys_bo *_bo);
static int
radv_amdgpu_bo_va_op(struct radv_amdgpu_winsys *ws, amdgpu_bo_handle bo, uint64_t offset, uint64_t size, uint64_t addr,
radv_amdgpu_bo_va_op(struct radv_amdgpu_winsys *ws, uint32_t bo_handle, uint64_t offset, uint64_t size, uint64_t addr,
uint32_t bo_flags, uint64_t internal_flags, uint32_t ops)
{
uint64_t flags = internal_flags;
if (bo) {
if (bo_handle) {
flags = AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_EXECUTABLE;
if ((bo_flags & RADEON_FLAG_VA_UNCACHED) && ws->info.gfx_level >= GFX9)
@ -46,7 +47,7 @@ radv_amdgpu_bo_va_op(struct radv_amdgpu_winsys *ws, amdgpu_bo_handle bo, uint64_
size = align64(size, getpagesize());
return amdgpu_bo_va_op_raw(ws->dev, bo, offset, size, addr, flags, ops);
return ac_drm_bo_va_op_raw(ws->fd, bo_handle, offset, size, addr, flags, ops);
}
static int
@ -115,10 +116,10 @@ radv_amdgpu_winsys_bo_virtual_bind(struct radeon_winsys *_ws, struct radeon_wins
* will first unmap all existing VA that overlap the requested range and then map.
*/
if (bo) {
r = radv_amdgpu_bo_va_op(ws, bo->bo, bo_offset, size, parent->base.va + offset, 0, 0, AMDGPU_VA_OP_REPLACE);
} else {
r =
radv_amdgpu_bo_va_op(ws, NULL, 0, size, parent->base.va + offset, 0, AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_REPLACE);
radv_amdgpu_bo_va_op(ws, bo->bo_handle, bo_offset, size, parent->base.va + offset, 0, 0, AMDGPU_VA_OP_REPLACE);
} else {
r = radv_amdgpu_bo_va_op(ws, 0, 0, size, parent->base.va + offset, 0, AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_REPLACE);
}
if (r) {
@ -311,7 +312,7 @@ radv_amdgpu_winsys_bo_destroy(struct radeon_winsys *_ws, struct radeon_winsys_bo
int r;
/* Clear mappings of this PRT VA region. */
r = radv_amdgpu_bo_va_op(ws, NULL, 0, bo->base.size, bo->base.va, 0, 0, AMDGPU_VA_OP_CLEAR);
r = radv_amdgpu_bo_va_op(ws, 0, 0, bo->base.size, bo->base.va, 0, 0, AMDGPU_VA_OP_CLEAR);
if (r) {
fprintf(stderr, "radv/amdgpu: Failed to clear a PRT VA region (%d).\n", r);
}
@ -325,7 +326,7 @@ radv_amdgpu_winsys_bo_destroy(struct radeon_winsys *_ws, struct radeon_winsys_bo
if (ws->debug_all_bos)
radv_amdgpu_global_bo_list_del(ws, bo);
radv_amdgpu_bo_va_op(ws, bo->bo, 0, bo->base.size, bo->base.va, 0, 0, AMDGPU_VA_OP_UNMAP);
radv_amdgpu_bo_va_op(ws, bo->bo_handle, 0, bo->base.size, bo->base.va, 0, 0, AMDGPU_VA_OP_UNMAP);
amdgpu_bo_free(bo->bo);
}
@ -407,7 +408,7 @@ radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws, uint64_t size, unsigned
bo->ranges[0].bo_offset = 0;
/* Reserve a PRT VA region. */
r = radv_amdgpu_bo_va_op(ws, NULL, 0, size, bo->base.va, 0, AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_MAP);
r = radv_amdgpu_bo_va_op(ws, 0, 0, size, bo->base.va, 0, AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_MAP);
if (r) {
fprintf(stderr, "radv/amdgpu: Failed to reserve a PRT VA region (%d).\n", r);
result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
@ -485,21 +486,23 @@ radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws, uint64_t size, unsigned
goto error_bo_alloc;
}
r = radv_amdgpu_bo_va_op(ws, buf_handle, 0, size, va, flags, 0, AMDGPU_VA_OP_MAP);
uint32_t kms_handle = 0;
r = amdgpu_bo_export(buf_handle, amdgpu_bo_handle_type_kms, &kms_handle);
assert(!r);
r = radv_amdgpu_bo_va_op(ws, kms_handle, 0, size, va, flags, 0, AMDGPU_VA_OP_MAP);
if (r) {
result = VK_ERROR_UNKNOWN;
goto error_va_map;
}
bo->bo = buf_handle;
bo->bo_handle = kms_handle;
bo->base.initial_domain = initial_domain;
bo->base.use_global_list = false;
bo->priority = priority;
bo->cpu_map = NULL;
r = amdgpu_bo_export(buf_handle, amdgpu_bo_handle_type_kms, &bo->bo_handle);
assert(!r);
if (initial_domain & RADEON_DOMAIN_VRAM) {
/* Buffers allocated in VRAM with the NO_CPU_ACCESS flag
* aren't mappable and they are counted as part of the VRAM
@ -555,13 +558,12 @@ radv_amdgpu_winsys_bo_map(struct radeon_winsys *_ws, struct radeon_winsys_bo *_b
memset(&args, 0, sizeof(args));
args.in.handle = bo->bo_handle;
int ret =
drmCommandWriteRead(amdgpu_device_get_fd(radv_amdgpu_winsys(_ws)->dev), DRM_AMDGPU_GEM_MMAP, &args, sizeof(args));
int ret = drmCommandWriteRead(radv_amdgpu_winsys(_ws)->fd, DRM_AMDGPU_GEM_MMAP, &args, sizeof(args));
if (ret)
return NULL;
void *data = mmap(fixed_addr, bo->base.size, PROT_READ | PROT_WRITE, MAP_SHARED | (use_fixed_addr ? MAP_FIXED : 0),
amdgpu_device_get_fd(radv_amdgpu_winsys(_ws)->dev), args.out.addr_ptr);
radv_amdgpu_winsys(_ws)->fd, args.out.addr_ptr);
if (data == MAP_FAILED)
return NULL;
@ -650,7 +652,11 @@ radv_amdgpu_winsys_bo_from_ptr(struct radeon_winsys *_ws, void *pointer, uint64_
goto error_va_alloc;
}
if (amdgpu_bo_va_op(buf_handle, 0, size, va, 0, AMDGPU_VA_OP_MAP)) {
uint32_t kms_handle = 0;
ASSERTED int r = amdgpu_bo_export(buf_handle, amdgpu_bo_handle_type_kms, &kms_handle);
assert(!r);
if (ac_drm_bo_va_op(ws->fd, kms_handle, 0, size, va, 0, AMDGPU_VA_OP_MAP)) {
result = VK_ERROR_UNKNOWN;
goto error_va_map;
}
@ -660,14 +666,12 @@ radv_amdgpu_winsys_bo_from_ptr(struct radeon_winsys *_ws, void *pointer, uint64_
bo->va_handle = va_handle;
bo->base.size = size;
bo->bo = buf_handle;
bo->bo_handle = kms_handle;
bo->base.initial_domain = RADEON_DOMAIN_GTT;
bo->base.use_global_list = false;
bo->priority = priority;
bo->cpu_map = NULL;
ASSERTED int r = amdgpu_bo_export(buf_handle, amdgpu_bo_handle_type_kms, &bo->bo_handle);
assert(!r);
p_atomic_add(&ws->allocated_gtt, align64(bo->base.size, ws->info.gart_page_size));
if (ws->debug_all_bos)
@ -717,7 +721,11 @@ radv_amdgpu_winsys_bo_from_fd(struct radeon_winsys *_ws, int fd, unsigned priori
goto error;
}
r = amdgpu_bo_query_info(result.buf_handle, &info);
uint32_t kms_handle = 0;
r = amdgpu_bo_export(result.buf_handle, amdgpu_bo_handle_type_kms, &kms_handle);
assert(!r);
r = ac_drm_bo_query_info(ws->fd, kms_handle, &info);
if (r) {
vk_result = VK_ERROR_UNKNOWN;
goto error_query;
@ -734,7 +742,7 @@ radv_amdgpu_winsys_bo_from_fd(struct radeon_winsys *_ws, int fd, unsigned priori
goto error_query;
}
r = radv_amdgpu_bo_va_op(ws, result.buf_handle, 0, result.alloc_size, va, 0, 0, AMDGPU_VA_OP_MAP);
r = radv_amdgpu_bo_va_op(ws, kms_handle, 0, result.alloc_size, va, 0, 0, AMDGPU_VA_OP_MAP);
if (r) {
vk_result = VK_ERROR_UNKNOWN;
goto error_va_map;
@ -746,6 +754,7 @@ radv_amdgpu_winsys_bo_from_fd(struct radeon_winsys *_ws, int fd, unsigned priori
initial |= RADEON_DOMAIN_GTT;
bo->bo = result.buf_handle;
bo->bo_handle = kms_handle;
bo->base.va = va;
bo->va_handle = va_handle;
bo->base.initial_domain = initial;
@ -754,9 +763,6 @@ radv_amdgpu_winsys_bo_from_fd(struct radeon_winsys *_ws, int fd, unsigned priori
bo->priority = priority;
bo->cpu_map = NULL;
r = amdgpu_bo_export(result.buf_handle, amdgpu_bo_handle_type_kms, &bo->bo_handle);
assert(!r);
if (bo->base.initial_domain & RADEON_DOMAIN_VRAM)
p_atomic_add(&ws->allocated_vram, align64(bo->base.size, ws->info.gart_page_size));
if (bo->base.initial_domain & RADEON_DOMAIN_GTT)
@ -810,7 +816,11 @@ radv_amdgpu_bo_get_flags_from_fd(struct radeon_winsys *_ws, int fd, enum radeon_
if (r)
return false;
r = amdgpu_bo_query_info(result.buf_handle, &info);
uint32_t kms_handle = 0;
r = amdgpu_bo_export(result.buf_handle, amdgpu_bo_handle_type_kms, &kms_handle);
assert(!r);
r = ac_drm_bo_query_info(ws->fd, kms_handle, &info);
amdgpu_bo_free(result.buf_handle);
if (r)
return false;
@ -937,7 +947,7 @@ radv_amdgpu_winsys_bo_set_metadata(struct radeon_winsys *_ws, struct radeon_wins
metadata.size_metadata = md->size_metadata;
memcpy(metadata.umd_metadata, md->metadata, sizeof(md->metadata));
amdgpu_bo_set_metadata(bo->bo, &metadata);
ac_drm_bo_set_metadata(ws->fd, bo->bo_handle, &metadata);
}
static void
@ -948,7 +958,7 @@ radv_amdgpu_winsys_bo_get_metadata(struct radeon_winsys *_ws, struct radeon_wins
struct radv_amdgpu_winsys_bo *bo = radv_amdgpu_winsys_bo(_bo);
struct amdgpu_bo_info info = {0};
int r = amdgpu_bo_query_info(bo->bo, &info);
int r = ac_drm_bo_query_info(ws->fd, bo->bo_handle, &info);
if (r)
return;

51
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
View file

@ -16,6 +16,7 @@
#include "util/os_time.h"
#include "util/u_memory.h"
#include "ac_debug.h"
#include "ac_linux_drm.h"
#include "radv_amdgpu_bo.h"
#include "radv_amdgpu_cs.h"
#include "radv_amdgpu_winsys.h"
@ -160,7 +161,6 @@ static void
radv_amdgpu_request_to_fence(struct radv_amdgpu_ctx *ctx, struct radv_amdgpu_fence *fence,
struct radv_amdgpu_cs_request *req)
{
fence->fence.context = ctx->ctx;
fence->fence.ip_type = req->ip_type;
fence->fence.ip_instance = req->ip_instance;
fence->fence.ring = req->ring;
@ -1227,13 +1227,13 @@ radv_amdgpu_cs_submit_zero(struct radv_amdgpu_ctx *ctx, enum amd_ip_type ip_type
if (sem_info->wait.syncobj_count || sem_info->wait.timeline_syncobj_count) {
int fd;
ret = amdgpu_cs_syncobj_export_sync_file(ctx->ws->dev, queue_syncobj, &fd);
ret = ac_drm_cs_syncobj_export_sync_file(ctx->ws->fd, queue_syncobj, &fd);
if (ret < 0)
return VK_ERROR_DEVICE_LOST;
for (unsigned i = 0; i < sem_info->wait.syncobj_count; ++i) {
int fd2;
ret = amdgpu_cs_syncobj_export_sync_file(ctx->ws->dev, sem_info->wait.syncobj[i], &fd2);
ret = ac_drm_cs_syncobj_export_sync_file(ctx->ws->fd, sem_info->wait.syncobj[i], &fd2);
if (ret < 0) {
close(fd);
return VK_ERROR_DEVICE_LOST;
@ -1244,15 +1244,15 @@ radv_amdgpu_cs_submit_zero(struct radv_amdgpu_ctx *ctx, enum amd_ip_type ip_type
}
for (unsigned i = 0; i < sem_info->wait.timeline_syncobj_count; ++i) {
int fd2;
ret = amdgpu_cs_syncobj_export_sync_file2(
ctx->ws->dev, sem_info->wait.syncobj[i + sem_info->wait.syncobj_count], sem_info->wait.points[i], 0, &fd2);
ret = ac_drm_cs_syncobj_export_sync_file2(
ctx->ws->fd, sem_info->wait.syncobj[i + sem_info->wait.syncobj_count], sem_info->wait.points[i], 0, &fd2);
if (ret < 0) {
/* This works around a kernel bug where the fence isn't copied if it is already
* signalled. Since it is already signalled it is totally fine to not wait on it.
*
* kernel patch: https://patchwork.freedesktop.org/patch/465583/ */
uint64_t point;
ret = amdgpu_cs_syncobj_query2(ctx->ws->dev, &sem_info->wait.syncobj[i + sem_info->wait.syncobj_count],
ret = ac_drm_cs_syncobj_query2(ctx->ws->fd, &sem_info->wait.syncobj[i + sem_info->wait.syncobj_count],
&point, 1, 0);
if (!ret && point >= sem_info->wait.points[i])
continue;
@ -1264,7 +1264,7 @@ radv_amdgpu_cs_submit_zero(struct radv_amdgpu_ctx *ctx, enum amd_ip_type ip_type
sync_accumulate("radv", &fd, fd2);
close(fd2);
}
ret = amdgpu_cs_syncobj_import_sync_file(ctx->ws->dev, queue_syncobj, fd);
ret = ac_drm_cs_syncobj_import_sync_file(ctx->ws->fd, queue_syncobj, fd);
close(fd);
if (ret < 0)
return VK_ERROR_DEVICE_LOST;
@ -1277,23 +1277,23 @@ radv_amdgpu_cs_submit_zero(struct radv_amdgpu_ctx *ctx, enum amd_ip_type ip_type
uint32_t src_handle = queue_syncobj;
if (ctx->ws->info.has_timeline_syncobj) {
ret = amdgpu_cs_syncobj_transfer(ctx->ws->dev, dst_handle, 0, src_handle, 0, 0);
ret = ac_drm_cs_syncobj_transfer(ctx->ws->fd, dst_handle, 0, src_handle, 0, 0);
if (ret < 0)
return VK_ERROR_DEVICE_LOST;
} else {
int fd;
ret = amdgpu_cs_syncobj_export_sync_file(ctx->ws->dev, src_handle, &fd);
ret = ac_drm_cs_syncobj_export_sync_file(ctx->ws->fd, src_handle, &fd);
if (ret < 0)
return VK_ERROR_DEVICE_LOST;
ret = amdgpu_cs_syncobj_import_sync_file(ctx->ws->dev, dst_handle, fd);
ret = ac_drm_cs_syncobj_import_sync_file(ctx->ws->fd, dst_handle, fd);
close(fd);
if (ret < 0)
return VK_ERROR_DEVICE_LOST;
}
}
for (unsigned i = 0; i < sem_info->signal.timeline_syncobj_count; ++i) {
ret = amdgpu_cs_syncobj_transfer(ctx->ws->dev, sem_info->signal.syncobj[i + sem_info->signal.syncobj_count],
ret = ac_drm_cs_syncobj_transfer(ctx->ws->fd, sem_info->signal.syncobj[i + sem_info->signal.syncobj_count],
sem_info->signal.points[i], queue_syncobj, 0, 0);
if (ret < 0)
return VK_ERROR_DEVICE_LOST;
@ -1576,7 +1576,7 @@ radv_amdgpu_ctx_create(struct radeon_winsys *_ws, enum radeon_ctx_priority prior
if (!ctx)
return VK_ERROR_OUT_OF_HOST_MEMORY;
r = amdgpu_cs_ctx_create2(ws->dev, amdgpu_priority, &ctx->ctx);
r = ac_drm_cs_ctx_create2(ws->fd, amdgpu_priority, &ctx->ctx_handle);
if (r && r == -EACCES) {
result = VK_ERROR_NOT_PERMITTED_KHR;
goto fail_create;
@ -1599,7 +1599,7 @@ radv_amdgpu_ctx_create(struct radeon_winsys *_ws, enum radeon_ctx_priority prior
return VK_SUCCESS;
fail_alloc:
amdgpu_cs_ctx_free(ctx->ctx);
ac_drm_cs_ctx_free(ws->fd, ctx->ctx_handle);
fail_create:
FREE(ctx);
return result;
@ -1613,12 +1613,12 @@ radv_amdgpu_ctx_destroy(struct radeon_winsys_ctx *rwctx)
for (unsigned ip = 0; ip <= AMDGPU_HW_IP_NUM; ++ip) {
for (unsigned ring = 0; ring < MAX_RINGS_PER_TYPE; ++ring) {
if (ctx->queue_syncobj[ip][ring])
amdgpu_cs_destroy_syncobj(ctx->ws->dev, ctx->queue_syncobj[ip][ring]);
ac_drm_cs_destroy_syncobj(ctx->ws->fd, ctx->queue_syncobj[ip][ring]);
}
}
ctx->ws->base.buffer_destroy(&ctx->ws->base, ctx->fence_bo);
amdgpu_cs_ctx_free(ctx->ctx);
ac_drm_cs_ctx_free(ctx->ws->fd, ctx->ctx_handle);
FREE(ctx);
}
@ -1627,7 +1627,7 @@ radv_amdgpu_ctx_queue_syncobj(struct radv_amdgpu_ctx *ctx, unsigned ip, unsigned
{
uint32_t *syncobj = &ctx->queue_syncobj[ip][ring];
if (!*syncobj) {
amdgpu_cs_create_syncobj2(ctx->ws->dev, DRM_SYNCOBJ_CREATE_SIGNALED, syncobj);
ac_drm_cs_create_syncobj2(ctx->ws->fd, DRM_SYNCOBJ_CREATE_SIGNALED, syncobj);
}
return *syncobj;
}
@ -1639,8 +1639,11 @@ radv_amdgpu_ctx_wait_idle(struct radeon_winsys_ctx *rwctx, enum amd_ip_type ip_t
if (ctx->last_submission[ip_type][ring_index].fence.fence) {
uint32_t expired;
int ret =
amdgpu_cs_query_fence_status(&ctx->last_submission[ip_type][ring_index].fence, 1000000000ull, 0, &expired);
int ret = ac_drm_cs_query_fence_status(
ctx->ws->fd, ctx->ctx_handle, ctx->last_submission[ip_type][ring_index].fence.ip_type,
ctx->last_submission[ip_type][ring_index].fence.ip_instance,
ctx->last_submission[ip_type][ring_index].fence.ring, ctx->last_submission[ip_type][ring_index].fence.fence,
1000000000ull, 0, &expired);
if (ret || !expired)
return false;
@ -1676,7 +1679,7 @@ radv_amdgpu_ctx_set_pstate(struct radeon_winsys_ctx *rwctx, enum radeon_ctx_psta
uint32_t current_pstate = 0;
int r;
r = amdgpu_cs_ctx_stable_pstate(ctx->ctx, AMDGPU_CTX_OP_GET_STABLE_PSTATE, 0, &current_pstate);
r = ac_drm_cs_ctx_stable_pstate(ctx->ws->fd, ctx->ctx_handle, AMDGPU_CTX_OP_GET_STABLE_PSTATE, 0, &current_pstate);
if (r) {
fprintf(stderr, "radv/amdgpu: failed to get current pstate\n");
return r;
@ -1688,7 +1691,7 @@ radv_amdgpu_ctx_set_pstate(struct radeon_winsys_ctx *rwctx, enum radeon_ctx_psta
if (current_pstate == new_pstate)
return 0;
r = amdgpu_cs_ctx_stable_pstate(ctx->ctx, AMDGPU_CTX_OP_SET_STABLE_PSTATE, new_pstate, NULL);
r = ac_drm_cs_ctx_stable_pstate(ctx->ws->fd, ctx->ctx_handle, AMDGPU_CTX_OP_SET_STABLE_PSTATE, new_pstate, NULL);
if (r) {
fprintf(stderr, "radv/amdgpu: failed to set new pstate\n");
return r;
@ -1825,16 +1828,14 @@ radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx, struct radv_amdgpu_cs_request
chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4;
chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
struct amdgpu_cs_fence_info fence_info;
fence_info.handle = radv_amdgpu_winsys_bo(ctx->fence_bo)->bo;
/* Need to reserve 4 QWORD for user fence:
* QWORD[0]: completed fence
* QWORD[1]: preempted fence
* QWORD[2]: reset fence
* QWORD[3]: preempted then reset
*/
fence_info.offset = (request->ip_type * MAX_RINGS_PER_TYPE + request->ring) * 4;
amdgpu_cs_chunk_fence_info_to_data(&fence_info, &chunk_data[i]);
uint32_t offset = (request->ip_type * MAX_RINGS_PER_TYPE + request->ring) * 4;
ac_drm_cs_chunk_fence_info_to_data(radv_amdgpu_winsys_bo(ctx->fence_bo)->bo_handle, offset, &chunk_data[i]);
}
if (sem_info->cs_emit_wait &&
@ -1895,7 +1896,7 @@ radv_amdgpu_cs_submit(struct radv_amdgpu_ctx *ctx, struct radv_amdgpu_cs_request
if (r == -ENOMEM)
os_time_sleep(1000);
r = amdgpu_cs_submit_raw2(ctx->ws->dev, ctx->ctx, 0, num_chunks, chunks, &request->seq_no);
r = ac_drm_cs_submit_raw2(ctx->ws->fd, ctx->ctx_handle, 0, num_chunks, chunks, &request->seq_no);
} while (r == -ENOMEM && os_time_get_nano() < abs_timeout_ns);
if (r) {

2
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.h
View file

@ -28,7 +28,7 @@ struct radv_amdgpu_fence {
struct radv_amdgpu_ctx {
struct radv_amdgpu_winsys *ws;
amdgpu_context_handle ctx;
uint32_t ctx_handle;
struct radv_amdgpu_fence last_submission[AMDGPU_HW_IP_NUM + 1][MAX_RINGS_PER_TYPE];
struct radeon_winsys_bo *fence_bo;

36
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
View file

@ -13,6 +13,7 @@
#include <stdlib.h>
#include <string.h>
#include "drm-uapi/amdgpu_drm.h"
#include "ac_linux_drm.h"
#include "ac_surface.h"
#include "radv_amdgpu_bo.h"
#include "radv_amdgpu_cs.h"
@ -56,7 +57,7 @@ static uint64_t
radv_amdgpu_winsys_query_value(struct radeon_winsys *rws, enum radeon_value_id value)
{
struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
struct amdgpu_heap_info heap;
struct amdgpu_heap_info heap = {0};
uint64_t retval = 0;
switch (value) {
@ -67,34 +68,34 @@ radv_amdgpu_winsys_query_value(struct radeon_winsys *rws, enum radeon_value_id v
case RADEON_ALLOCATED_GTT:
return ws->allocated_gtt;
case RADEON_TIMESTAMP:
amdgpu_query_info(ws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
ac_drm_query_info(ws->fd, AMDGPU_INFO_TIMESTAMP, 8, &retval);
return retval;
case RADEON_NUM_BYTES_MOVED:
amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
ac_drm_query_info(ws->fd, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
return retval;
case RADEON_NUM_EVICTIONS:
amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
ac_drm_query_info(ws->fd, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
return retval;
case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
amdgpu_query_info(ws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS, 8, &retval);
ac_drm_query_info(ws->fd, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS, 8, &retval);
return retval;
case RADEON_VRAM_USAGE:
amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
ac_drm_query_heap_info(ws->fd, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
return heap.heap_usage;
case RADEON_VRAM_VIS_USAGE:
amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &heap);
ac_drm_query_heap_info(ws->fd, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &heap);
return heap.heap_usage;
case RADEON_GTT_USAGE:
amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
ac_drm_query_heap_info(ws->fd, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
return heap.heap_usage;
case RADEON_GPU_TEMPERATURE:
amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval);
ac_drm_query_sensor_info(ws->fd, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval);
return retval;
case RADEON_CURRENT_SCLK:
amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval);
ac_drm_query_sensor_info(ws->fd, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval);
return retval;
case RADEON_CURRENT_MCLK:
amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval);
ac_drm_query_sensor_info(ws->fd, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval);
return retval;
default:
unreachable("invalid query value");
@ -108,7 +109,7 @@ radv_amdgpu_winsys_read_registers(struct radeon_winsys *rws, unsigned reg_offset
{
struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers, 0xffffffff, 0, out) == 0;
return ac_drm_read_mm_registers(ws->fd, reg_offset / 4, num_registers, 0xffffffff, 0, out) == 0;
}
static const char *
@ -126,7 +127,7 @@ radv_amdgpu_winsys_query_gpuvm_fault(struct radeon_winsys *rws, struct radv_wins
struct drm_amdgpu_info_gpuvm_fault gpuvm_fault = {0};
int r;
r = amdgpu_query_info(ws->dev, AMDGPU_INFO_GPUVM_FAULT, sizeof(gpuvm_fault), &gpuvm_fault);
r = ac_drm_query_info(ws->fd, AMDGPU_INFO_GPUVM_FAULT, sizeof(gpuvm_fault), &gpuvm_fault);
if (r < 0) {
fprintf(stderr, "radv/amdgpu: Failed to query the last GPUVM fault (%d).\n", r);
return false;
@ -173,7 +174,7 @@ radv_amdgpu_winsys_destroy(struct radeon_winsys *rws)
free(ws->global_bo_list.bos);
if (ws->reserve_vmid)
amdgpu_vm_unreserve_vmid(ws->dev, 0);
ac_drm_vm_unreserve_vmid(ws->fd, 0);
u_rwlock_destroy(&ws->log_bo_list_lock);
amdgpu_device_deinitialize(ws->dev);
@ -184,7 +185,7 @@ static int
radv_amdgpu_winsys_get_fd(struct radeon_winsys *rws)
{
struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys *)rws;
return amdgpu_device_get_fd(ws->dev);
return ws->fd;
}
static const struct vk_sync_type *const *
@ -247,6 +248,7 @@ radv_amdgpu_winsys_create(int fd, uint64_t debug_flags, uint64_t perftest_flags,
ws->refcount = 1;
ws->dev = dev;
ws->fd = amdgpu_device_get_fd(dev);
ws->info.drm_major = drm_major;
ws->info.drm_minor = drm_minor;
if (!do_winsys_init(ws, fd))
@ -259,7 +261,7 @@ radv_amdgpu_winsys_create(int fd, uint64_t debug_flags, uint64_t perftest_flags,
ws->reserve_vmid = reserve_vmid;
if (ws->reserve_vmid) {
r = amdgpu_vm_reserve_vmid(dev, 0);
r = ac_drm_vm_reserve_vmid(ws->fd, 0);
if (r) {
fprintf(stderr, "radv/amdgpu: failed to reserve vmid.\n");
goto winsys_fail;
@ -267,7 +269,7 @@ radv_amdgpu_winsys_create(int fd, uint64_t debug_flags, uint64_t perftest_flags,
}
int num_sync_types = 0;
ws->syncobj_sync_type = vk_drm_syncobj_get_type(amdgpu_device_get_fd(ws->dev));
ws->syncobj_sync_type = vk_drm_syncobj_get_type(ws->fd);
if (ws->syncobj_sync_type.features) {
/* multi wait is always supported */
ws->syncobj_sync_type.features |= VK_SYNC_FEATURE_GPU_MULTI_WAIT;

1
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h
View file

@ -24,6 +24,7 @@
struct radv_amdgpu_winsys {
struct radeon_winsys base;
amdgpu_device_handle dev;
int fd;
struct radeon_info info;

41
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
View file

@ -102,7 +102,7 @@ static bool amdgpu_bo_wait(struct radeon_winsys *rws,
bool buffer_busy = true;
int r;
r = amdgpu_bo_wait_for_idle(get_real_bo(bo)->bo_handle, timeout, &buffer_busy);
r = ac_drm_bo_wait_for_idle(aws->fd, get_real_bo(bo)->kms_handle, timeout, &buffer_busy);
if (r)
fprintf(stderr, "%s: amdgpu_bo_wait_for_idle failed %i\n", __func__, r);
@ -180,7 +180,7 @@ void amdgpu_bo_destroy(struct amdgpu_winsys *aws, struct pb_buffer_lean *_buf)
_mesa_hash_table_remove_key(aws->bo_export_table, bo->bo_handle);
if (bo->b.base.placement & RADEON_DOMAIN_VRAM_GTT) {
amdgpu_bo_va_op(bo->bo_handle, 0, bo->b.base.size,
ac_drm_bo_va_op(aws->fd, bo->kms_handle, 0, bo->b.base.size,
amdgpu_va_get_start_addr(bo->va_handle), 0, AMDGPU_VA_OP_UNMAP);
amdgpu_va_range_free(bo->va_handle);
}
@ -572,6 +572,9 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *aws,
goto error_bo_alloc;
}
uint32_t kms_handle = 0;
amdgpu_bo_export(buf_handle, amdgpu_bo_handle_type_kms, &kms_handle);
if (initial_domain & RADEON_DOMAIN_VRAM_GTT) {
unsigned va_gap_size = aws->check_vm ? MAX2(4 * alignment, 64 * 1024) : 0;
@ -590,7 +593,7 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *aws,
if (flags & RADEON_FLAG_GL2_BYPASS)
vm_flags |= AMDGPU_VM_MTYPE_UC;
r = amdgpu_bo_va_op_raw(aws->dev, buf_handle, 0, size, va, vm_flags, AMDGPU_VA_OP_MAP);
r = ac_drm_bo_va_op_raw(aws->fd, kms_handle, 0, size, va, vm_flags, AMDGPU_VA_OP_MAP);
if (r)
goto error_va_map;
}
@ -604,13 +607,13 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *aws,
bo->b.unique_id = __sync_fetch_and_add(&aws->next_bo_unique_id, 1);
bo->bo_handle = buf_handle;
bo->va_handle = va_handle;
bo->kms_handle = kms_handle;
if (initial_domain & RADEON_DOMAIN_VRAM)
aws->allocated_vram += align64(size, aws->info.gart_page_size);
else if (initial_domain & RADEON_DOMAIN_GTT)
aws->allocated_gtt += align64(size, aws->info.gart_page_size);
amdgpu_bo_export(bo->bo_handle, amdgpu_bo_handle_type_kms, &bo->kms_handle);
amdgpu_add_buffer_to_global_list(aws, bo);
return &bo->b;
@ -1029,7 +1032,7 @@ static void amdgpu_bo_sparse_destroy(struct radeon_winsys *rws, struct pb_buffer
struct amdgpu_bo_sparse *bo = get_sparse_bo(amdgpu_winsys_bo(_buf));
int r;
r = amdgpu_bo_va_op_raw(aws->dev, NULL, 0,
r = ac_drm_bo_va_op_raw(aws->fd, 0, 0,
(uint64_t)bo->num_va_pages * RADEON_SPARSE_PAGE_SIZE,
amdgpu_va_get_start_addr(bo->va_handle), 0, AMDGPU_VA_OP_CLEAR);
if (r) {
@ -1096,7 +1099,7 @@ amdgpu_bo_sparse_create(struct amdgpu_winsys *aws, uint64_t size,
if (r)
goto error_va_alloc;
r = amdgpu_bo_va_op_raw(aws->dev, NULL, 0, map_size, gpu_address,
r = ac_drm_bo_va_op_raw(aws->fd, 0, 0, map_size, gpu_address,
AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_MAP);
if (r)
goto error_va_map;
@ -1166,7 +1169,7 @@ amdgpu_bo_sparse_commit(struct radeon_winsys *rws, struct pb_buffer_lean *buf,
goto out;
}
r = amdgpu_bo_va_op_raw(aws->dev, backing->bo->bo_handle,
r = ac_drm_bo_va_op_raw(aws->fd, backing->bo->kms_handle,
(uint64_t)backing_start * RADEON_SPARSE_PAGE_SIZE,
(uint64_t)backing_size * RADEON_SPARSE_PAGE_SIZE,
amdgpu_va_get_start_addr(bo->va_handle) +
@ -1193,7 +1196,7 @@ amdgpu_bo_sparse_commit(struct radeon_winsys *rws, struct pb_buffer_lean *buf,
}
}
} else {
r = amdgpu_bo_va_op_raw(aws->dev, NULL, 0,
r = ac_drm_bo_va_op_raw(aws->fd, 0, 0,
(uint64_t)(end_va_page - va_page) * RADEON_SPARSE_PAGE_SIZE,
amdgpu_va_get_start_addr(bo->va_handle) +
(uint64_t)va_page * RADEON_SPARSE_PAGE_SIZE,
@ -1309,7 +1312,7 @@ static void amdgpu_buffer_get_metadata(struct radeon_winsys *rws,
enum amd_gfx_level gfx_level = aws->info.gfx_level;
int r;
r = amdgpu_bo_query_info(bo->bo_handle, &info);
r = ac_drm_bo_query_info(aws->fd, bo->kms_handle, &info);
if (r)
return;
@ -1348,7 +1351,7 @@ static void amdgpu_buffer_set_metadata(struct radeon_winsys *rws,
metadata.size_metadata = md->size_metadata;
memcpy(metadata.umd_metadata, md->metadata, sizeof(md->metadata));
amdgpu_bo_set_metadata(real->bo_handle, &metadata);
ac_drm_bo_set_metadata(aws->fd, real->kms_handle, &metadata);
}
struct pb_buffer_lean *
@ -1540,8 +1543,11 @@ static struct pb_buffer_lean *amdgpu_bo_from_handle(struct radeon_winsys *rws,
return &bo->b.base;
}
uint32_t kms_handle;
amdgpu_bo_export(result.buf_handle, amdgpu_bo_handle_type_kms, &kms_handle);
/* Get initial domains. */
r = amdgpu_bo_query_info(result.buf_handle, &info);
r = ac_drm_bo_query_info(aws->fd, kms_handle, &info);
if (r)
goto error;
@ -1557,7 +1563,7 @@ static struct pb_buffer_lean *amdgpu_bo_from_handle(struct radeon_winsys *rws,
if (!bo)
goto error;
r = amdgpu_bo_va_op_raw(aws->dev, result.buf_handle, 0, result.alloc_size, va,
r = ac_drm_bo_va_op_raw(aws->fd, kms_handle, 0, result.alloc_size, va,
AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE |
AMDGPU_VM_PAGE_EXECUTABLE |
(is_prime_linear_buffer ? AMDGPU_VM_MTYPE_UC : 0),
@ -1596,6 +1602,7 @@ static struct pb_buffer_lean *amdgpu_bo_from_handle(struct radeon_winsys *rws,
simple_mtx_init(&bo->map_lock, mtx_plain);
bo->bo_handle = result.buf_handle;
bo->va_handle = va_handle;
bo->kms_handle = kms_handle;
bo->is_shared = true;
if (bo->b.base.placement & RADEON_DOMAIN_VRAM)
@ -1603,8 +1610,6 @@ static struct pb_buffer_lean *amdgpu_bo_from_handle(struct radeon_winsys *rws,
else if (bo->b.base.placement & RADEON_DOMAIN_GTT)
aws->allocated_gtt += align64(bo->b.base.size, aws->info.gart_page_size);
amdgpu_bo_export(bo->bo_handle, amdgpu_bo_handle_type_kms, &bo->kms_handle);
amdgpu_add_buffer_to_global_list(aws, bo);
_mesa_hash_table_insert(aws->bo_export_table, bo->bo_handle, bo);
@ -1735,7 +1740,10 @@ static struct pb_buffer_lean *amdgpu_bo_from_ptr(struct radeon_winsys *rws,
0, &va, &va_handle, AMDGPU_VA_RANGE_HIGH))
goto error_va_alloc;
if (amdgpu_bo_va_op(buf_handle, 0, aligned_size, va, 0, AMDGPU_VA_OP_MAP))
uint32_t kms_handle;
amdgpu_bo_export(buf_handle, amdgpu_bo_handle_type_kms, &kms_handle);
if (ac_drm_bo_va_op(aws->fd, kms_handle, 0, aligned_size, va, 0, AMDGPU_VA_OP_MAP))
goto error_va_map;
/* Initialize it. */
@ -1750,13 +1758,12 @@ static struct pb_buffer_lean *amdgpu_bo_from_ptr(struct radeon_winsys *rws,
bo->bo_handle = buf_handle;
bo->cpu_ptr = pointer;
bo->va_handle = va_handle;
bo->kms_handle = kms_handle;
aws->allocated_gtt += aligned_size;
amdgpu_add_buffer_to_global_list(aws, bo);
amdgpu_bo_export(bo->bo_handle, amdgpu_bo_handle_type_kms, &bo->kms_handle);
return (struct pb_buffer_lean*)bo;
error_va_map:

49
src/gallium/winsys/amdgpu/drm/amdgpu_cs.cpp
View file

@ -27,7 +27,7 @@
void amdgpu_fence_destroy(struct amdgpu_fence *fence)
{
amdgpu_cs_destroy_syncobj(fence->aws->dev, fence->syncobj);
ac_drm_cs_destroy_syncobj(fence->aws->fd, fence->syncobj);
if (fence->ctx)
amdgpu_ctx_reference(&fence->ctx, NULL);
@ -47,7 +47,7 @@ amdgpu_fence_create(struct amdgpu_cs *cs)
amdgpu_ctx_reference(&fence->ctx, ctx);
fence->ctx = ctx;
fence->ip_type = cs->ip_type;
if (amdgpu_cs_create_syncobj2(ctx->aws->dev, 0, &fence->syncobj)) {
if (ac_drm_cs_create_syncobj2(ctx->aws->fd, 0, &fence->syncobj)) {
free(fence);
return NULL;
}
@ -72,7 +72,7 @@ amdgpu_fence_import_syncobj(struct radeon_winsys *rws, int fd)
fence->aws = aws;
fence->ip_type = 0xffffffff;
r = amdgpu_cs_import_syncobj(aws->dev, fd, &fence->syncobj);
r = ac_drm_cs_import_syncobj(aws->fd, fd, &fence->syncobj);
if (r) {
FREE(fence);
return NULL;
@ -98,15 +98,15 @@ amdgpu_fence_import_sync_file(struct radeon_winsys *rws, int fd)
/* fence->ctx == NULL means that the fence is syncobj-based. */
/* Convert sync_file into syncobj. */
int r = amdgpu_cs_create_syncobj(aws->dev, &fence->syncobj);
int r = ac_drm_cs_create_syncobj(aws->fd, &fence->syncobj);
if (r) {
FREE(fence);
return NULL;
}
r = amdgpu_cs_syncobj_import_sync_file(aws->dev, fence->syncobj, fd);
r = ac_drm_cs_syncobj_import_sync_file(aws->fd, fence->syncobj, fd);
if (r) {
amdgpu_cs_destroy_syncobj(aws->dev, fence->syncobj);
ac_drm_cs_destroy_syncobj(aws->fd, fence->syncobj);
FREE(fence);
return NULL;
}
@ -127,7 +127,7 @@ static int amdgpu_fence_export_sync_file(struct radeon_winsys *rws,
util_queue_fence_wait(&fence->submitted);
/* Convert syncobj into sync_file. */
r = amdgpu_cs_syncobj_export_sync_file(aws->dev, fence->syncobj, &fd);
r = ac_drm_cs_syncobj_export_sync_file(aws->fd, fence->syncobj, &fd);
return r ? -1 : fd;
}
@ -137,18 +137,18 @@ static int amdgpu_export_signalled_sync_file(struct radeon_winsys *rws)
uint32_t syncobj;
int fd = -1;
int r = amdgpu_cs_create_syncobj2(aws->dev, DRM_SYNCOBJ_CREATE_SIGNALED,
int r = ac_drm_cs_create_syncobj2(aws->fd, DRM_SYNCOBJ_CREATE_SIGNALED,
&syncobj);
if (r) {
return -1;
}
r = amdgpu_cs_syncobj_export_sync_file(aws->dev, syncobj, &fd);
r = ac_drm_cs_syncobj_export_sync_file(aws->fd, syncobj, &fd);
if (r) {
fd = -1;
}
amdgpu_cs_destroy_syncobj(aws->dev, syncobj);
ac_drm_cs_destroy_syncobj(aws->fd, syncobj);
return fd;
}
@ -207,7 +207,7 @@ bool amdgpu_fence_wait(struct pipe_fence_handle *fence, uint64_t timeout,
if ((uint64_t)abs_timeout == OS_TIMEOUT_INFINITE)
abs_timeout = INT64_MAX;
if (amdgpu_cs_syncobj_wait(afence->aws->dev, &afence->syncobj, 1,
if (ac_drm_cs_syncobj_wait(afence->aws->fd, &afence->syncobj, 1,
abs_timeout, 0, NULL))
return false;
@ -281,7 +281,7 @@ static struct radeon_winsys_ctx *amdgpu_ctx_create(struct radeon_winsys *rws,
ctx->reference.count = 1;
ctx->allow_context_lost = allow_context_lost;
r = amdgpu_cs_ctx_create2(ctx->aws->dev, amdgpu_priority, &ctx->ctx);
r = ac_drm_cs_ctx_create2(ctx->aws->fd, amdgpu_priority, &ctx->ctx_handle);
if (r) {
fprintf(stderr, "amdgpu: amdgpu_cs_ctx_create2 failed. (%i)\n", r);
goto error_create;
@ -305,13 +305,14 @@ static struct radeon_winsys_ctx *amdgpu_ctx_create(struct radeon_winsys *rws,
memset(ctx->user_fence_cpu_address_base, 0, alloc_buffer.alloc_size);
ctx->user_fence_bo = buf_handle;
amdgpu_bo_export(buf_handle, amdgpu_bo_handle_type_kms, &ctx->user_fence_bo_kms_handle);
return (struct radeon_winsys_ctx*)ctx;
error_user_fence_map:
amdgpu_bo_free(buf_handle);
error_user_fence_alloc:
amdgpu_cs_ctx_free(ctx->ctx);
ac_drm_cs_ctx_free(ctx->aws->fd, ctx->ctx_handle);
error_create:
FREE(ctx);
return NULL;
@ -368,8 +369,8 @@ static int amdgpu_submit_gfx_nop(struct amdgpu_ctx *ctx)
* it by submitting a no-op job. If it reports an error, then assume
* that the reset is not complete.
*/
amdgpu_context_handle temp_ctx;
r = amdgpu_cs_ctx_create2(ctx->aws->dev, AMDGPU_CTX_PRIORITY_NORMAL, &temp_ctx);
uint32_t temp_ctx_handle;
r = ac_drm_cs_ctx_create2(ctx->aws->fd, AMDGPU_CTX_PRIORITY_NORMAL, &temp_ctx_handle);
if (r)
return r;
@ -380,13 +381,16 @@ static int amdgpu_submit_gfx_nop(struct amdgpu_ctx *ctx)
if (r)
goto destroy_ctx;
uint32_t kms_handle;
amdgpu_bo_export(buf_handle, amdgpu_bo_handle_type_kms, &kms_handle);
r = amdgpu_va_range_alloc(ctx->aws->dev, amdgpu_gpu_va_range_general,
request.alloc_size, request.phys_alignment,
0, &va, &va_handle,
AMDGPU_VA_RANGE_32_BIT | AMDGPU_VA_RANGE_HIGH);
if (r)
goto destroy_bo;
r = amdgpu_bo_va_op_raw(ctx->aws->dev, buf_handle, 0, request.alloc_size, va,
r = ac_drm_bo_va_op_raw(ctx->aws->fd, kms_handle, 0, request.alloc_size, va,
AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE,
AMDGPU_VA_OP_MAP);
if (r)
@ -421,14 +425,14 @@ static int amdgpu_submit_gfx_nop(struct amdgpu_ctx *ctx)
chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
chunks[1].chunk_data = (uintptr_t)&ib_in;
r = amdgpu_cs_submit_raw2(ctx->aws->dev, temp_ctx, 0, 2, chunks, &seq_no);
r = ac_drm_cs_submit_raw2(ctx->aws->fd, temp_ctx_handle, 0, 2, chunks, &seq_no);
destroy_bo:
if (va_handle)
amdgpu_va_range_free(va_handle);
amdgpu_bo_free(buf_handle);
destroy_ctx:
amdgpu_cs_ctx_free(temp_ctx);
ac_drm_cs_ctx_free(ctx->aws->fd, temp_ctx_handle);
return r;
}
@ -488,7 +492,7 @@ amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx *rwctx, bool full_reset_o
* that the context reset is complete.
*/
if (ctx->sw_status != PIPE_NO_RESET) {
int r = amdgpu_cs_query_reset_state2(ctx->ctx, &flags);
int r = ac_drm_cs_query_reset_state2(ctx->aws->fd, ctx->ctx_handle, &flags);
if (!r) {
if (flags & AMDGPU_CTX_QUERY2_FLAGS_RESET) {
if (reset_completed) {
@ -927,10 +931,7 @@ amdgpu_cs_create(struct radeon_cmdbuf *rcs,
assert(cs->queue_index < AMDGPU_MAX_QUEUES);
}
struct amdgpu_cs_fence_info fence_info;
fence_info.handle = cs->ctx->user_fence_bo;
fence_info.offset = cs->ip_type * 4;
amdgpu_cs_chunk_fence_info_to_data(&fence_info,
ac_drm_cs_chunk_fence_info_to_data(cs->ctx->user_fence_bo_kms_handle, cs->ip_type * 4,
(struct drm_amdgpu_cs_chunk_data*)&cs->fence_chunk);
if (!amdgpu_init_cs_context(ctx->aws, &cs->csc1, ip_type)) {
@ -1628,7 +1629,7 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
if (r == -ENOMEM)
os_time_sleep(1000);
r = amdgpu_cs_submit_raw2(aws->dev, acs->ctx->ctx, 0, num_chunks, chunks, &seq_no);
r = ac_drm_cs_submit_raw2(aws->fd, acs->ctx->ctx_handle, 0, num_chunks, chunks, &seq_no);
} while (r == -ENOMEM);
if (!r) {

6
src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
View file

@ -10,6 +10,7 @@
#include "amdgpu_bo.h"
#include "util/u_memory.h"
#include "ac_linux_drm.h"
#include "drm-uapi/amdgpu_drm.h"
#ifdef __cplusplus
@ -24,9 +25,10 @@ extern "C" {
struct amdgpu_ctx {
struct pipe_reference reference;
uint32_t ctx_handle;
struct amdgpu_winsys *aws;
amdgpu_context_handle ctx;
amdgpu_bo_handle user_fence_bo;
uint32_t user_fence_bo_kms_handle;
uint64_t *user_fence_cpu_address_base;
/* If true, report lost contexts and skip command submission.
@ -191,7 +193,7 @@ static inline void amdgpu_ctx_reference(struct amdgpu_ctx **dst, struct amdgpu_c
if (pipe_reference(old_dst ? &old_dst->reference : NULL,
src ? &src->reference : NULL)) {
amdgpu_cs_ctx_free(old_dst->ctx);
ac_drm_cs_ctx_free(old_dst->aws->fd, old_dst->ctx_handle);
amdgpu_bo_cpu_unmap(old_dst->user_fence_bo);
amdgpu_bo_free(old_dst->user_fence_bo);
FREE(old_dst);

30
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
View file

@ -71,7 +71,7 @@ fail:
static void do_winsys_deinit(struct amdgpu_winsys *aws)
{
if (aws->reserve_vmid)
amdgpu_vm_unreserve_vmid(aws->dev, 0);
ac_drm_vm_unreserve_vmid(aws->fd, 0);
for (unsigned i = 0; i < ARRAY_SIZE(aws->queues); i++) {
for (unsigned j = 0; j < ARRAY_SIZE(aws->queues[i].fences); j++)
@ -156,7 +156,7 @@ static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
enum radeon_value_id value)
{
struct amdgpu_winsys *aws = amdgpu_winsys(rws);
struct amdgpu_heap_info heap;
struct amdgpu_heap_info heap = {0};
uint64_t retval = 0;
switch (value) {
@ -177,7 +177,7 @@ static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
case RADEON_NUM_MAPPED_BUFFERS:
return aws->num_mapped_buffers;
case RADEON_TIMESTAMP:
amdgpu_query_info(aws->dev, AMDGPU_INFO_TIMESTAMP, 8, &retval);
ac_drm_query_info(aws->fd, AMDGPU_INFO_TIMESTAMP, 8, &retval);
return retval;
case RADEON_NUM_GFX_IBS:
return aws->num_gfx_IBs;
@ -188,32 +188,32 @@ static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
case RADEON_GFX_IB_SIZE_COUNTER:
return aws->gfx_ib_size_counter;
case RADEON_NUM_BYTES_MOVED:
amdgpu_query_info(aws->dev, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
ac_drm_query_info(aws->fd, AMDGPU_INFO_NUM_BYTES_MOVED, 8, &retval);
return retval;
case RADEON_NUM_EVICTIONS:
amdgpu_query_info(aws->dev, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
ac_drm_query_info(aws->fd, AMDGPU_INFO_NUM_EVICTIONS, 8, &retval);
return retval;
case RADEON_NUM_VRAM_CPU_PAGE_FAULTS:
amdgpu_query_info(aws->dev, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS, 8, &retval);
ac_drm_query_info(aws->fd, AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS, 8, &retval);
return retval;
case RADEON_VRAM_USAGE:
amdgpu_query_heap_info(aws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
ac_drm_query_heap_info(aws->fd, AMDGPU_GEM_DOMAIN_VRAM, 0, &heap);
return heap.heap_usage;
case RADEON_VRAM_VIS_USAGE:
amdgpu_query_heap_info(aws->dev, AMDGPU_GEM_DOMAIN_VRAM,
ac_drm_query_heap_info(aws->fd, AMDGPU_GEM_DOMAIN_VRAM,
AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &heap);
return heap.heap_usage;
case RADEON_GTT_USAGE:
amdgpu_query_heap_info(aws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
ac_drm_query_heap_info(aws->fd, AMDGPU_GEM_DOMAIN_GTT, 0, &heap);
return heap.heap_usage;
case RADEON_GPU_TEMPERATURE:
amdgpu_query_sensor_info(aws->dev, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval);
ac_drm_query_sensor_info(aws->fd, AMDGPU_INFO_SENSOR_GPU_TEMP, 4, &retval);
return retval;
case RADEON_CURRENT_SCLK:
amdgpu_query_sensor_info(aws->dev, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval);
ac_drm_query_sensor_info(aws->fd, AMDGPU_INFO_SENSOR_GFX_SCLK, 4, &retval);
return retval;
case RADEON_CURRENT_MCLK:
amdgpu_query_sensor_info(aws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval);
ac_drm_query_sensor_info(aws->fd, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval);
return retval;
case RADEON_CS_THREAD_TIME:
return util_queue_get_thread_time_nano(&aws->cs_queue, 0);
@ -227,7 +227,7 @@ static bool amdgpu_read_registers(struct radeon_winsys *rws,
{
struct amdgpu_winsys *aws = amdgpu_winsys(rws);
return amdgpu_read_mm_registers(aws->dev, reg_offset / 4, num_registers,
return ac_drm_read_mm_registers(aws->fd, reg_offset / 4, num_registers,
0xffffffff, 0, out) == 0;
}
@ -325,7 +325,7 @@ amdgpu_cs_set_pstate(struct radeon_cmdbuf *rcs, enum radeon_ctx_pstate pstate)
return false;
uint32_t amdgpu_pstate = radeon_to_amdgpu_pstate(pstate);
return amdgpu_cs_ctx_stable_pstate(cs->ctx->ctx,
return ac_drm_cs_ctx_stable_pstate(cs->aws->fd, cs->ctx->ctx_handle,
AMDGPU_CTX_OP_SET_STABLE_PSTATE, amdgpu_pstate, NULL) == 0;
}
@ -505,7 +505,7 @@ amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
_mesa_hash_table_insert(dev_tab, dev, aws);
if (aws->reserve_vmid) {
r = amdgpu_vm_reserve_vmid(dev, 0);
r = ac_drm_vm_reserve_vmid(aws->fd, 0);
if (r) {
amdgpu_winsys_destroy_locked(&sws->base, true);
simple_mtx_unlock(&dev_tab_mutex);