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radv: Only copy the render area from VRS to HTILE

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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15587>
This commit is contained in:
Jason Ekstrand 2022-08-30 10:44:43 -05:00 • committed by Marge Bot
parent c7d0d328d5
commit 0461d59098
3 changed files with 23 additions and 22 deletions
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24
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -6110,11 +6110,6 @@ radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer, uint32_t subpa
struct radv_image *ds_image = ds_iview->image;
uint32_t level = ds_iview->vk.base_mip_level;
VkExtent2D extent = {
.width = radv_minify(ds_image->info.width, level),
.height = radv_minify(ds_image->info.height, level),
};
/* HTILE buffer */
uint64_t htile_offset = ds_image->bindings[0].offset + ds_image->planes[0].surface.meta_offset +
ds_image->planes[0].surface.u.gfx9.meta_levels[level].offset;
@ -6123,28 +6118,31 @@ radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer, uint32_t subpa
radv_buffer_init(&htile_buffer, cmd_buffer->device, ds_image->bindings[0].bo, htile_size, htile_offset);
assert(state->render_area.offset.x + state->render_area.extent.width <= ds_image->info.width &&
state->render_area.offset.x + state->render_area.extent.height <= ds_image->info.height);
/* Copy the VRS rates to the HTILE buffer. */
radv_copy_vrs_htile(cmd_buffer, vrs_iview->image, &extent, ds_image, &htile_buffer, true);
radv_copy_vrs_htile(cmd_buffer, vrs_iview->image, &state->render_area, ds_image,
&htile_buffer, true);
radv_buffer_finish(&htile_buffer);
} else {
/* When a subpass uses a VRS attachment without binding a depth/stencil attachment, we have
* to copy the VRS rates to our internal HTILE buffer.
*/
struct vk_framebuffer *fb = cmd_buffer->state.framebuffer;
struct radv_image *ds_image = radv_cmd_buffer_get_vrs_image(cmd_buffer);
if (ds_image) {
if (ds_image && state->render_area.offset.x < ds_image->info.width &&
state->render_area.offset.y < ds_image->info.height) {
/* HTILE buffer */
struct radv_buffer *htile_buffer = cmd_buffer->device->vrs.buffer;
VkExtent2D extent = {
.width = MIN2(fb->width, ds_image->info.width),
.height = MIN2(fb->height, ds_image->info.height),
};
VkRect2D area = state->render_area;
area.extent.width = MIN2(area.extent.width, ds_image->info.width - area.offset.x);
area.extent.height = MIN2(area.extent.height, ds_image->info.height - area.offset.y);
/* Copy the VRS rates to the HTILE buffer. */
radv_copy_vrs_htile(cmd_buffer, vrs_iview->image, &extent, ds_image, htile_buffer, false);
radv_copy_vrs_htile(cmd_buffer, vrs_iview->image, &area, ds_image, htile_buffer, false);
}
}
}

2
src/amd/vulkan/radv_meta.h
View file

@ -192,7 +192,7 @@ void radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *imag
void radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
const VkImageSubresourceRange *subresourceRange);
void radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_image,
VkExtent2D *extent, struct radv_image *dst_image,
const VkRect2D *rect, struct radv_image *dst_image,
struct radv_buffer *htile_buffer, bool read_htile_value);
bool radv_can_use_fmask_copy(struct radv_cmd_buffer *cmd_buffer,

19
src/amd/vulkan/radv_meta_copy_vrs_htile.c
View file

@ -51,11 +51,13 @@ build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf
/* Get coordinates. */
nir_ssa_def *global_id = get_global_ids(&b, 2);
nir_ssa_def *offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 8);
/* Multiply the coordinates by the HTILE block size. */
nir_ssa_def *coord = nir_imul_imm(&b, global_id, 8);
nir_ssa_def *coord = nir_iadd(&b, nir_imul_imm(&b, global_id, 8), offset);
/* Load constants. */
nir_ssa_def *constants = nir_load_push_constant(&b, 3, 32, nir_imm_int(&b, 0), .range = 12);
nir_ssa_def *constants = nir_load_push_constant(&b, 3, 32, nir_imm_int(&b, 8), .range = 20);
nir_ssa_def *htile_pitch = nir_channel(&b, constants, 0);
nir_ssa_def *htile_slice_size = nir_channel(&b, constants, 1);
nir_ssa_def *read_htile_value = nir_channel(&b, constants, 2);
@ -176,7 +178,7 @@ radv_device_init_meta_copy_vrs_htile_state(struct radv_device *device,
&(VkPushConstantRange){
VK_SHADER_STAGE_COMPUTE_BIT,
0,
12,
20,
},
};
@ -210,7 +212,7 @@ fail:
void
radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_image,
VkExtent2D *extent, struct radv_image *dst_image,
const VkRect2D *rect, struct radv_image *dst_image,
struct radv_buffer *htile_buffer, bool read_htile_value)
{
struct radv_device *device = cmd_buffer->device;
@ -280,16 +282,17 @@ radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *vrs_i
.offset = 0,
.range = htile_buffer->vk.size}}});
const unsigned constants[3] = {
const unsigned constants[5] = {
rect->offset.x, rect->offset.y,
dst_image->planes[0].surface.meta_pitch, dst_image->planes[0].surface.meta_slice_size,
read_htile_value,
};
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), state->copy_vrs_htile_p_layout,
VK_SHADER_STAGE_COMPUTE_BIT, 0, 12, constants);
VK_SHADER_STAGE_COMPUTE_BIT, 0, 20, constants);
uint32_t width = DIV_ROUND_UP(extent->width, 8);
uint32_t height = DIV_ROUND_UP(extent->height, 8);
uint32_t width = DIV_ROUND_UP(rect->extent.width, 8);
uint32_t height = DIV_ROUND_UP(rect->extent.height, 8);
radv_unaligned_dispatch(cmd_buffer, width, height, 1);