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radeonsi: move sparse intrinsic lowering to a separate file, call it later
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38802>
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commit
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5 changed files with 40 additions and 32 deletions
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@ -51,6 +51,7 @@ files_libradeonsi = files(
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'si_nir_kill_outputs.c',
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'si_nir_lower_abi.c',
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'si_nir_lower_color_inputs_to_sysvals.c',
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'si_nir_lower_intrinsics_early.c',
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'si_nir_lower_polygon_stipple.c',
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'si_nir_lower_ps_color_inputs.c',
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'si_nir_lower_resource.c',
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36
src/gallium/drivers/radeonsi/si_nir_lower_intrinsics_early.c
Normal file
36
src/gallium/drivers/radeonsi/si_nir_lower_intrinsics_early.c
Normal file
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@ -0,0 +1,36 @@
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/* Copyright 2025 Advanced Micro Devices, Inc.
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* SPDX-License-Identifier: MIT
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*/
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#include "si_shader_internal.h"
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#include "nir_builder.h"
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static bool
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lower_intrinsic_filter(const nir_instr *instr, const void *dummy)
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{
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return instr->type == nir_instr_type_intrinsic;
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}
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static nir_def *
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lower_intrinsic_instr(nir_builder *b, nir_instr *instr, void *dummy)
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{
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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switch (intrin->intrinsic) {
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case nir_intrinsic_is_sparse_texels_resident:
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/* code==0 means sparse texels are resident */
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return nir_ieq_imm(b, intrin->src[0].ssa, 0);
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case nir_intrinsic_sparse_residency_code_and:
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return nir_ior(b, intrin->src[0].ssa, intrin->src[1].ssa);
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default:
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return NULL;
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}
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}
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bool si_nir_lower_intrinsics_early(nir_shader *nir)
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{
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return nir_shader_lower_instructions(nir,
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lower_intrinsic_filter,
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lower_intrinsic_instr,
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NULL);
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}
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@ -647,6 +647,8 @@ static void si_preprocess_nir(struct si_nir_shader_ctx *ctx)
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NIR_PASS(progress, nir, ac_nir_lower_mesh_inputs_to_mem);
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}
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NIR_PASS(progress, nir, si_nir_lower_intrinsics_early);
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if (mesa_shader_stage_is_compute(nir->info.stage)) {
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/* gl_LocalInvocationIndex must be derived from gl_LocalInvocationID.xyz to make it correct
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* with quad derivatives. Using gl_SubgroupID for that (which is what we do by default) is
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@ -125,6 +125,7 @@ nir_def *si_nir_load_internal_binding(struct si_screen *sscreen, nir_builder *b,
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unsigned num_components);
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bool si_nir_lower_abi(nir_shader *nir, struct si_shader *shader, struct si_shader_args *args);
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bool si_nir_lower_color_inputs_to_sysvals(nir_shader *nir);
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bool si_nir_lower_intrinsics_early(nir_shader *nir);
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bool si_nir_lower_polygon_stipple(nir_shader *nir);
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bool si_nir_lower_ps_color_inputs(nir_shader *nir, const union si_shader_key *key,
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const struct si_shader_info *info);
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@ -107,36 +107,6 @@ void si_nir_late_opts(nir_shader *nir)
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}
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}
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static bool
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lower_intrinsic_filter(const nir_instr *instr, const void *dummy)
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{
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return instr->type == nir_instr_type_intrinsic;
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}
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static nir_def *
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lower_intrinsic_instr(nir_builder *b, nir_instr *instr, void *dummy)
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{
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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switch (intrin->intrinsic) {
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case nir_intrinsic_is_sparse_texels_resident:
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/* code==0 means sparse texels are resident */
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return nir_ieq_imm(b, intrin->src[0].ssa, 0);
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case nir_intrinsic_sparse_residency_code_and:
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return nir_ior(b, intrin->src[0].ssa, intrin->src[1].ssa);
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default:
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return NULL;
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}
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}
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static bool si_lower_intrinsics(nir_shader *nir)
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{
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return nir_shader_lower_instructions(nir,
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lower_intrinsic_filter,
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lower_intrinsic_instr,
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NULL);
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}
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/**
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* Perform "lowering" operations on the NIR that are run once when the shader
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* selector is created.
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@ -169,8 +139,6 @@ static void si_lower_nir(struct si_screen *sscreen, struct nir_shader *nir)
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};
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NIR_PASS(_, nir, nir_lower_image, &lower_image_options);
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NIR_PASS(_, nir, si_lower_intrinsics);
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NIR_PASS(_, nir, ac_nir_lower_sin_cos);
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/* Lower load constants to scalar and then clean up the mess */
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