diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 2e12d7da09c..246f3be9bff 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -171,18 +171,16 @@ emit_mbcnt(isel_context* ctx, Temp dst, Operand mask = Operand(), Operand base =
 Temp
 emit_wqm(Builder& bld, Temp src, Temp dst = Temp(0, s1), bool program_needs_wqm = false)
 {
-   if (bld.program->stage != fragment_fs) {
-      if (!dst.id())
-         return src;
-      else
-         return bld.copy(Definition(dst), src);
-   } else if (!dst.id()) {
-      dst = bld.tmp(src.regClass());
+   if (dst.id())
+      bld.copy(Definition(dst), src);
+   else
+      dst = src;
+
+   if (bld.program->stage == fragment_fs) {
+      bld.pseudo(aco_opcode::p_wqm);
+      bld.program->needs_wqm |= program_needs_wqm;
    }
 
-   assert(src.bytes() == dst.bytes());
-   bld.pseudo(aco_opcode::p_wqm, Definition(dst), src);
-   bld.program->needs_wqm |= program_needs_wqm;
    return dst;
 }
 
diff --git a/src/amd/compiler/aco_lower_to_hw_instr.cpp b/src/amd/compiler/aco_lower_to_hw_instr.cpp
index ed22671bb52..ba49e3817b6 100644
--- a/src/amd/compiler/aco_lower_to_hw_instr.cpp
+++ b/src/amd/compiler/aco_lower_to_hw_instr.cpp
@@ -2395,8 +2395,7 @@ lower_to_hw_instr(Program* program)
                handle_operands(copy_operations, &ctx, program->gfx_level, pi);
                break;
             }
-            case aco_opcode::p_parallelcopy:
-            case aco_opcode::p_wqm: {
+            case aco_opcode::p_parallelcopy: {
                std::map<PhysReg, copy_operation> copy_operations;
                for (unsigned j = 0; j < instr->operands.size(); j++) {
                   assert(instr->definitions[j].bytes() == instr->operands[j].bytes());
diff --git a/src/amd/compiler/aco_optimizer.cpp b/src/amd/compiler/aco_optimizer.cpp
index f8a2322603f..dfe7b5c4a78 100644
--- a/src/amd/compiler/aco_optimizer.cpp
+++ b/src/amd/compiler/aco_optimizer.cpp
@@ -662,7 +662,6 @@ alu_can_accept_constant(const aco_ptr<Instruction>& instr, unsigned operand)
    case aco_opcode::v_cndmask_b32: return operand != 2;
    case aco_opcode::s_addk_i32:
    case aco_opcode::s_mulk_i32:
-   case aco_opcode::p_wqm:
    case aco_opcode::p_extract_vector:
    case aco_opcode::p_split_vector:
    case aco_opcode::v_readlane_b32:
@@ -2071,11 +2070,6 @@ label_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr)
          instr->operands[2].setTemp(ctx.info[instr->operands[2].tempId()].temp);
       }
       break;
-   case aco_opcode::p_wqm:
-      if (instr->operands[0].isTemp() && ctx.info[instr->operands[0].tempId()].is_scc_invert()) {
-         ctx.info[instr->definitions[0].tempId()].set_temp(instr->operands[0].getTemp());
-      }
-      break;
    case aco_opcode::s_mul_i32:
       /* Testing every uint32_t shows that 0x3f800000*n is never a denormal.
        * This pattern is created from a uniform nir_op_b2f. */
@@ -4787,13 +4781,6 @@ select_instruction(opt_ctx& ctx, aco_ptr<Instruction>& instr)
                instr->opcode == aco_opcode::s_cselect_b32) &&
               instr->operands[2].isTemp()) {
       ctx.info[instr->operands[2].tempId()].set_scc_needed();
-   } else if (instr->opcode == aco_opcode::p_wqm && instr->operands[0].isTemp() &&
-              ctx.info[instr->definitions[0].tempId()].is_scc_needed()) {
-      /* Propagate label so it is correctly detected by the uniform bool transform */
-      ctx.info[instr->operands[0].tempId()].set_scc_needed();
-
-      /* Fix definition to SCC, this will prevent RA from adding superfluous moves */
-      instr->definitions[0].setFixed(scc);
    }
 
    /* check for literals */
diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp
index 7c4535b26e2..1acd899e6c5 100644
--- a/src/amd/compiler/aco_register_allocation.cpp
+++ b/src/amd/compiler/aco_register_allocation.cpp
@@ -1888,7 +1888,6 @@ handle_pseudo(ra_ctx& ctx, const RegisterFile& reg_file, Instruction* instr)
    case aco_opcode::p_create_vector:
    case aco_opcode::p_split_vector:
    case aco_opcode::p_parallelcopy:
-   case aco_opcode::p_wqm:
    case aco_opcode::p_start_linear_vgpr: break;
    default: return;
    }
@@ -2942,8 +2941,7 @@ register_allocation(Program* program, std::vector<IDSet>& live_out_per_block, ra
                   if (get_reg_specified(ctx, register_file, rc, instr, reg))
                      definition->setFixed(reg);
                }
-            } else if (instr->opcode == aco_opcode::p_wqm ||
-                       instr->opcode == aco_opcode::p_parallelcopy ||
+            } else if (instr->opcode == aco_opcode::p_parallelcopy ||
                        (instr->opcode == aco_opcode::p_start_linear_vgpr &&
                         !instr->operands.empty())) {
                PhysReg reg = instr->operands[i].physReg();
diff --git a/src/amd/compiler/aco_validate.cpp b/src/amd/compiler/aco_validate.cpp
index 6b960a426a7..32c3d798dea 100644
--- a/src/amd/compiler/aco_validate.cpp
+++ b/src/amd/compiler/aco_validate.cpp
@@ -468,8 +468,7 @@ validate_ir(Program* program)
                      check(program->gfx_level >= GFX9 || !def.regClass().is_subdword(),
                            "Cannot split SGPR into subdword VGPRs before GFX9+", instr.get());
                }
-            } else if (instr->opcode == aco_opcode::p_parallelcopy ||
-                       instr->opcode == aco_opcode::p_wqm) {
+            } else if (instr->opcode == aco_opcode::p_parallelcopy) {
                check(instr->definitions.size() == instr->operands.size(),
                      "Number of Operands does not match number of Definitions", instr.get());
                for (unsigned i = 0; i < instr->operands.size(); i++) {