i965: Add INTEL_fragment_shader_ordering support.

Adds suppport for INTEL_fragment_shader_ordering. We achieve
the fragment ordering by using the same instruction as for
beginInvocationInterlockARB() which is by issuing a memory
fence via sendc.

Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>

docs/relnotes/18.3.0.html

@@ -59,6 +59,7 @@ Note: some of the new features are only available with certain drivers.
 <li>GL_EXT_vertex_attrib_64bit on i965, nvc0, radeonsi.</li>
 <li>GL_EXT_window_rectangles on radeonsi.</li>
 <li>GL_KHR_texture_compression_astc_sliced_3d on radeonsi.</li>
+<li>GL_INTEL_fragment_shader_ordering on i965.</li>
 <li>GL_NV_fragment_shader_interlock on i965.</li>
 </ul>
 

src/intel/compiler/brw_fs_nir.cpp

@@ -4836,6 +4836,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
       break;
    }
 
+   case nir_intrinsic_begin_fragment_shader_ordering:
    case nir_intrinsic_begin_invocation_interlock: {
       const fs_builder ubld = bld.group(8, 0);
       const fs_reg tmp = ubld.vgrf(BRW_REGISTER_TYPE_UD, 2);

src/mesa/drivers/dri/i965/intel_extensions.c

@@ -247,6 +247,7 @@ intelInitExtensions(struct gl_context *ctx)
       ctx->Extensions.OES_primitive_bounding_box = true;
       ctx->Extensions.OES_texture_buffer = true;
       ctx->Extensions.ARB_fragment_shader_interlock = true;
+      ctx->Extensions.INTEL_fragment_shader_ordering = true;
 
       if (can_do_pipelined_register_writes(brw->screen)) {
          ctx->Extensions.ARB_draw_indirect = true;