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gallium/ntt: Fix load_ubo_vec4 buffer index setup.
I had a funny +1 in nir_to_tgsi's load_ubo lowering on the buffer index, because I hadn't set lower_uniform_to_ubo for softpipe. This removes that weirdness in favor of just using lower_uniform_to_ubo, regardless of driver preference (which matters if a NIR-native driver had it set, and then the gallium draw module triggered the non-LLVM TGSI fallback path that hit NTT). Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8196>
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9789417055
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2 changed files with 6 additions and 27 deletions
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@ -274,7 +274,7 @@ ntt_setup_uniforms(struct ntt_compile *c)
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}
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nir_foreach_variable_with_modes(var, c->s, nir_var_mem_ubo) {
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ureg_DECL_constant2D(c->ureg, 0, 0, var->data.driver_location + 1);
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ureg_DECL_constant2D(c->ureg, 0, 0, var->data.driver_location);
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}
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for (int i = 0; i < PIPE_MAX_SAMPLERS; i++) {
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@ -984,16 +984,6 @@ ntt_ureg_src_dimension_indirect(struct ntt_compile *c, struct ureg_src usrc,
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}
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}
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static void
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ntt_emit_load_uniform(struct ntt_compile *c, nir_intrinsic_instr *instr)
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{
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struct ureg_src src =
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ntt_ureg_src_indirect(c, ureg_src_register(TGSI_FILE_CONSTANT,
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nir_intrinsic_base(instr)),
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instr->src[0]);
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ntt_store(c, &instr->dest, src);
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}
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/* Some load operations in NIR will have a fractional offset that we need to
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* swizzle down before storing to the result register.
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*/
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@ -1037,13 +1027,7 @@ ntt_emit_load_ubo_vec4(struct ntt_compile *c, nir_intrinsic_instr *instr)
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src = ntt_shift_by_frac(src, start_component,
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instr->num_components * bit_size / 32);
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if (nir_src_is_const(instr->src[0])) {
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src = ureg_src_dimension(src, nir_src_as_uint(instr->src[0]) + 1);
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} else {
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struct ureg_src block_index = ntt_get_src(c, instr->src[0]);
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src = ureg_src_dimension_indirect(src, ntt_reladdr(c, block_index), 1);
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}
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src = ntt_ureg_src_dimension_indirect(c, src, instr->src[0]);
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ntt_store(c, &instr->dest, src);
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}
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@ -1506,10 +1490,6 @@ static void
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ntt_emit_intrinsic(struct ntt_compile *c, nir_intrinsic_instr *instr)
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{
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switch (instr->intrinsic) {
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case nir_intrinsic_load_uniform:
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ntt_emit_load_uniform(c, instr);
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break;
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case nir_intrinsic_load_ubo:
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ntt_emit_load_ubo(c, instr);
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break;
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@ -2313,7 +2293,6 @@ nir_to_tgsi_lower_64bit_intrinsic(nir_builder *b, nir_intrinsic_instr *instr)
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b->cursor = nir_after_instr(&instr->instr);
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switch (instr->intrinsic) {
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case nir_intrinsic_load_uniform:
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case nir_intrinsic_load_ubo:
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case nir_intrinsic_load_ubo_vec4:
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case nir_intrinsic_load_ssbo:
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@ -2345,10 +2324,6 @@ nir_to_tgsi_lower_64bit_intrinsic(nir_builder *b, nir_intrinsic_instr *instr)
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nir_instr_as_intrinsic(nir_instr_clone(b->shader, &instr->instr));
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switch (instr->intrinsic) {
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case nir_intrinsic_load_uniform:
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nir_intrinsic_set_base(second, nir_intrinsic_base(second) + 1);
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break;
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case nir_intrinsic_load_ubo:
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case nir_intrinsic_load_ubo_vec4:
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case nir_intrinsic_load_ssbo:
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@ -2519,6 +2494,7 @@ ntt_fix_nir_options(struct nir_shader *s)
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!options->lower_flrp64 ||
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!options->lower_fmod ||
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!options->lower_rotate ||
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!options->lower_uniforms_to_ubo ||
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!options->lower_vector_cmp) {
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struct nir_shader_compiler_options *new_options =
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mem_dup(s->options, sizeof(*s->options));
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@ -2529,6 +2505,7 @@ ntt_fix_nir_options(struct nir_shader *s)
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new_options->lower_flrp64 = true;
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new_options->lower_fmod = true;
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new_options->lower_rotate = true;
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new_options->lower_uniforms_to_ubo = true,
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new_options->lower_vector_cmp = true;
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s->options = new_options;
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@ -2679,6 +2656,7 @@ static const nir_shader_compiler_options nir_to_tgsi_compiler_options = {
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.lower_fmod = true,
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.lower_rotate = true,
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.lower_sub = true,
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.lower_uniforms_to_ubo = true,
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.lower_vector_cmp = true,
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.use_interpolated_input_intrinsics = true,
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};
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@ -83,6 +83,7 @@ static const nir_shader_compiler_options sp_compiler_options = {
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.lower_fmod = true,
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.lower_rotate = true,
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.lower_sub = true,
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.lower_uniforms_to_ubo = true,
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.lower_vector_cmp = true,
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.use_interpolated_input_intrinsics = true,
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};
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