From 03847a6f0b19223d26efe900adf37728e0e758e3 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Mon, 5 Jan 2026 16:12:00 +0200 Subject: [PATCH] anv: remove snprintf for aux op transition With perfetto that string is processed later leading to use-after-free. Signed-off-by: Lionel Landwerlin Cc: mesa-stable Reviewed-by: Alyssa Rosenzweig (cherry picked from commit 413e169f453a6288f69880fd2ab4f0b7335089c4) Part-of: --- .pick_status.json | 2 +- src/intel/vulkan/genX_cmd_buffer.c | 50 ++++++++++++++---------------- 2 files changed, 25 insertions(+), 27 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index 9afa0abc069..bf162312420 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -174,7 +174,7 @@ "description": "anv: remove snprintf for aux op transition", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": null, "notes": null diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index e2cc13c415a..e0479d10331 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -3514,28 +3514,19 @@ aux_op_renders(enum isl_aux_op aux_op) static void add_pending_pipe_bits_for_color_aux_op(struct anv_cmd_buffer *cmd_buffer, enum isl_aux_op next_aux_op, - enum anv_pipe_bits pipe_bits) + enum anv_pipe_bits pipe_bits, + const char *reason) { const enum isl_aux_op last_aux_op = cmd_buffer->state.color_aux_op; assert(next_aux_op != last_aux_op); - char flush_reason[64] = {}; - if (INTEL_DEBUG(DEBUG_PIPE_CONTROL) || - u_trace_enabled(&cmd_buffer->device->ds.trace_context)) { - int ret = snprintf(flush_reason, sizeof(flush_reason), - "color aux-op: %s -> %s", - isl_aux_op_to_name(last_aux_op), - isl_aux_op_to_name(next_aux_op)); - assert(ret < sizeof(flush_reason)); - } - anv_add_pending_pipe_bits(cmd_buffer, aux_op_clears(next_aux_op) ? VK_PIPELINE_STAGE_2_NONE : VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT, aux_op_clears(next_aux_op) ? VK_PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT : 0, - pipe_bits, flush_reason); + pipe_bits, reason); } void @@ -3565,7 +3556,8 @@ genX(cmd_buffer_update_color_aux_op)(struct anv_cmd_buffer *cmd_buffer, * clear pass, to ensure correct ordering between pixels. */ add_pending_pipe_bits_for_color_aux_op( - cmd_buffer, next_aux_op, ANV_PIPE_RT_BTI_CHANGE); + cmd_buffer, next_aux_op, ANV_PIPE_RT_BTI_CHANGE, + "aux color !aux->aux"); #elif GFX_VERx10 == 125 /* From the ACM Bspec 47704 (r52663), "Render Target Fast Clear": @@ -3591,7 +3583,8 @@ genX(cmd_buffer_update_color_aux_op)(struct anv_cmd_buffer *cmd_buffer, ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_HDC_PIPELINE_FLUSH_BIT | ANV_PIPE_DATA_CACHE_FLUSH_BIT | - ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT); + ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT, + "aux color !aux->aux"); #elif GFX_VERx10 == 120 /* From the TGL Bspec 47704 (r52663), "Render Target Fast Clear": @@ -3614,7 +3607,8 @@ genX(cmd_buffer_update_color_aux_op)(struct anv_cmd_buffer *cmd_buffer, ANV_PIPE_DEPTH_STALL_BIT | ANV_PIPE_TILE_CACHE_FLUSH_BIT | ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | - ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT); + ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT, + "aux color !aux->aux"); #else /* From the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)": @@ -3642,9 +3636,9 @@ genX(cmd_buffer_update_color_aux_op)(struct anv_cmd_buffer *cmd_buffer, add_pending_pipe_bits_for_color_aux_op( cmd_buffer, next_aux_op, ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | - ANV_PIPE_END_OF_PIPE_SYNC_BIT); + ANV_PIPE_END_OF_PIPE_SYNC_BIT, + "aux color !aux->aux"); #endif - } else if (aux_op_clears(last_aux_op) && !aux_op_clears(next_aux_op)) { #if GFX_VERx10 >= 125 /* From the ACM PRM Vol. 9, "Color Fast Clear Synchronization": @@ -3656,7 +3650,8 @@ genX(cmd_buffer_update_color_aux_op)(struct anv_cmd_buffer *cmd_buffer, * RT flush = 1 */ add_pending_pipe_bits_for_color_aux_op( - cmd_buffer, next_aux_op, ANV_PIPE_RT_BTI_CHANGE); + cmd_buffer, next_aux_op, ANV_PIPE_RT_BTI_CHANGE, + "aux color aux->!aux"); #elif GFX_VERx10 == 120 /* From the TGL PRM Vol. 9, "Color Fast Clear Synchronization": @@ -3677,10 +3672,11 @@ genX(cmd_buffer_update_color_aux_op)(struct anv_cmd_buffer *cmd_buffer, * Replace the Tile Cache flush with an L3 fabric flush. */ add_pending_pipe_bits_for_color_aux_op( - cmd_buffer, next_aux_op, - ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | - ANV_PIPE_L3_FABRIC_FLUSH_BIT | - ANV_PIPE_DEPTH_STALL_BIT); + cmd_buffer, next_aux_op, + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | + ANV_PIPE_L3_FABRIC_FLUSH_BIT | + ANV_PIPE_DEPTH_STALL_BIT, + "aux color aux->!aux"); #else /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear": @@ -3696,9 +3692,10 @@ genX(cmd_buffer_update_color_aux_op)(struct anv_cmd_buffer *cmd_buffer, * synchronization. */ add_pending_pipe_bits_for_color_aux_op( - cmd_buffer, next_aux_op, - ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | - ANV_PIPE_END_OF_PIPE_SYNC_BIT); + cmd_buffer, next_aux_op, + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | + ANV_PIPE_END_OF_PIPE_SYNC_BIT, + "aux color aux->!aux"); #endif } else if (aux_op_renders(last_aux_op) != aux_op_renders(next_aux_op)) { @@ -3721,7 +3718,8 @@ genX(cmd_buffer_update_color_aux_op)(struct anv_cmd_buffer *cmd_buffer, add_pending_pipe_bits_for_color_aux_op( cmd_buffer, next_aux_op, ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | - ANV_PIPE_END_OF_PIPE_SYNC_BIT); + ANV_PIPE_END_OF_PIPE_SYNC_BIT, + "aux color render->!render"); } if (last_aux_op != ISL_AUX_OP_FAST_CLEAR &&