diff --git a/src/amd/vulkan/radv_spm.c b/src/amd/vulkan/radv_spm.c
index 9516f6306b9..bdea13957ff 100644
--- a/src/amd/vulkan/radv_spm.c
+++ b/src/amd/vulkan/radv_spm.c
@@ -65,6 +65,8 @@ radv_emit_spm_counters(struct radv_device *device, struct radeon_cmdbuf *cs, enu
    const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
    struct ac_spm *spm = &device->spm;
 
+   radeon_check_space(device->ws, cs, spm->num_used_sq_block_sel * 3);
+
    for (uint32_t b = 0; b < spm->num_used_sq_block_sel; b++) {
       struct ac_spm_block_select *sq_block_sel = &spm->sq_block_sel[b];
       const struct ac_spm_counter_select *cntr_sel = &sq_block_sel->counters[0];
@@ -78,6 +80,8 @@ radv_emit_spm_counters(struct radv_device *device, struct radeon_cmdbuf *cs, enu
       struct ac_spm_block_select *block_sel = &spm->block_sel[b];
       struct ac_pc_block_base *regs = block_sel->b->b->b;
 
+      radeon_check_space(device->ws, cs, 3 + (AC_SPM_MAX_COUNTER_PER_BLOCK * 6));
+
       radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, block_sel->grbm_gfx_index);
 
       for (unsigned c = 0; c < block_sel->num_counters; c++) {
@@ -113,6 +117,8 @@ radv_emit_spm_setup(struct radv_device *device, struct radeon_cmdbuf *cs, enum r
    assert(!(ring_size & (SPM_RING_BASE_ALIGN - 1)));
    assert(spm->sample_interval >= 32);
 
+   radeon_check_space(device->ws, cs, 27);
+
    /* Configure the SPM ring buffer. */
    radeon_set_uconfig_reg(cs, R_037200_RLC_SPM_PERFMON_CNTL,
                           S_037200_PERFMON_RING_MODE(0) | /* no stall and no interrupt on overflow */
@@ -158,6 +164,8 @@ radv_emit_spm_setup(struct radv_device *device, struct radeon_cmdbuf *cs, enum r
          rlc_muxsel_data = R_037220_RLC_SPM_SE_MUXSEL_DATA;
       }
 
+      radeon_check_space(device->ws, cs, 3 + spm->num_muxsel_lines[s] * (7 + AC_SPM_MUXSEL_LINE_SIZE));
+
       radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, grbm_gfx_index);
 
       for (unsigned l = 0; l < spm->num_muxsel_lines[s]; l++) {
diff --git a/src/amd/vulkan/radv_sqtt.c b/src/amd/vulkan/radv_sqtt.c
index 14f71723978..4e72271e4b1 100644
--- a/src/amd/vulkan/radv_sqtt.c
+++ b/src/amd/vulkan/radv_sqtt.c
@@ -81,6 +81,8 @@ radv_emit_sqtt_start(const struct radv_device *device, struct radeon_cmdbuf *cs,
    const unsigned shader_mask = ac_sqtt_get_shader_mask(rad_info);
    unsigned max_se = rad_info->max_se;
 
+   radeon_check_space(device->ws, cs, 6 + max_se * 33);
+
    for (unsigned se = 0; se < max_se; se++) {
       uint64_t va = radv_buffer_get_va(device->sqtt.bo);
       uint64_t data_va = ac_sqtt_get_data_va(rad_info, &device->sqtt, va, se);
@@ -307,6 +309,8 @@ radv_emit_sqtt_stop(const struct radv_device *device, struct radeon_cmdbuf *cs,
    const enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
    unsigned max_se = device->physical_device->rad_info.max_se;
 
+   radeon_check_space(device->ws, cs, 8 + max_se * 64);
+
    /* Stop the thread trace with a different event based on the queue. */
    if (qf == RADV_QUEUE_COMPUTE) {
       radeon_set_sh_reg(cs, R_00B878_COMPUTE_THREAD_TRACE_ENABLE, S_00B878_THREAD_TRACE_ENABLE(0));