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r600g: fix tex tile_type offset for cayman

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Noticed by taiu on IRC.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

(cherry picked from commit acca690c25)

Conflicts:

	src/gallium/drivers/r600/evergreen_state.c
This commit is contained in:
Alex Deucher 2012-02-10 10:49:13 -05:00 • committed by Michel Dänzer
parent e3943cf1cc
commit 036d999265
2 changed files with 8 additions and 1 deletions
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6
src/gallium/drivers/r600/evergreen_state.c
View file

@ -1046,6 +1046,7 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
struct pipe_resource *texture,
const struct pipe_sampler_view *state)
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
struct r600_pipe_resource_state *rstate;
struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
@ -1107,8 +1108,11 @@ static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_conte
rstate->val[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
S_030000_PITCH((pitch / 8) - 1) |
S_030000_NON_DISP_TILING_ORDER(tile_type) |
S_030000_TEX_WIDTH(texture->width0 - 1));
if (rctx->chip_class == CAYMAN)
rstate->val[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
else
rstate->val[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
rstate->val[1] = (S_030004_TEX_HEIGHT(height - 1) |
S_030004_TEX_DEPTH(depth - 1) |
S_030004_ARRAY_MODE(array_mode));

3
src/gallium/drivers/r600/evergreend.h
View file

@ -970,6 +970,9 @@
#define S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x1) << 5)
#define G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 5) & 0x1)
#define C_030000_NON_DISP_TILING_ORDER 0xFFFFFFDF
#define CM_S_030000_NON_DISP_TILING_ORDER(x) (((x) & 0x3) << 4)
#define CM_G_030000_NON_DISP_TILING_ORDER(x) (((x) >> 4) & 0x3)
#define CM_C_030000_NON_DISP_TILING_ORDER 0xFFFFFFCF
#define S_030000_PITCH(x) (((x) & 0xFFF) << 6)
#define G_030000_PITCH(x) (((x) >> 6) & 0xFFF)
#define C_030000_PITCH 0xFFFC003F