fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-02-01 13:20:25 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

mesa: rename OPCODE_INT -> OPCODE_TRUNC

Browse source 
Trunc is a more accurate description; there's no type conversion involved.
This commit is contained in:
Brian Paul 2008-11-06 17:14:33 -07:00
parent 517401af07
commit 035c0cf71a
5 changed files with 21 additions and 18 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
src/mesa/drivers/dri/i965/brw_wm_glsl.c
View file

@ -16,7 +16,7 @@ GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp)
struct prog_instruction *inst = &fp->Base.Instructions[i];
switch (inst->Opcode) {
case OPCODE_IF:
case OPCODE_INT:
case OPCODE_TRUNC:
case OPCODE_ENDIF:
case OPCODE_CAL:
case OPCODE_BRK:
@ -255,7 +255,7 @@ static void emit_abs( struct brw_wm_compile *c,
brw_set_saturate(p, 0);
}
static void emit_int( struct brw_wm_compile *c,
static void emit_trunc( struct brw_wm_compile *c,
struct prog_instruction *inst)
{
int i;
@ -1912,8 +1912,8 @@ static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
case OPCODE_LRP:
emit_lrp(c, inst);
break;
case OPCODE_INT:
emit_int(c, inst);
case OPCODE_TRUNC:
emit_trunc(c, inst);
break;
case OPCODE_MOV:
emit_mov(c, inst);

22
src/mesa/shader/prog_execute.c
View file

@ -789,17 +789,6 @@ _mesa_execute_program(GLcontext * ctx,
case OPCODE_ENDIF:
/* nothing */
break;
case OPCODE_INT: /* float to int */
{
GLfloat a[4], result[4];
fetch_vector4(&inst->SrcReg[0], machine, a);
result[0] = (GLfloat) (GLint) a[0];
result[1] = (GLfloat) (GLint) a[1];
result[2] = (GLfloat) (GLint) a[2];
result[3] = (GLfloat) (GLint) a[3];
store_vector4(inst, machine, result);
}
break;
case OPCODE_KIL_NV: /* NV_f_p only (conditional) */
if (eval_condition(machine, inst)) {
return GL_FALSE;
@ -1425,6 +1414,17 @@ _mesa_execute_program(GLcontext * ctx,
store_vector4(inst, machine, color);
}
break;
case OPCODE_TRUNC: /* truncate toward zero */
{
GLfloat a[4], result[4];
fetch_vector4(&inst->SrcReg[0], machine, a);
result[0] = (GLfloat) (GLint) a[0];
result[1] = (GLfloat) (GLint) a[1];
result[2] = (GLfloat) (GLint) a[2];
result[3] = (GLfloat) (GLint) a[3];
store_vector4(inst, machine, result);
}
break;
case OPCODE_UP2H: /* unpack two 16-bit floats */
{
GLfloat a[4], result[4];

2
src/mesa/shader/prog_instruction.c
View file

@ -182,7 +182,6 @@ static const struct instruction_info InstInfo[MAX_OPCODE] = {
{ OPCODE_FLR, "FLR", 1, 1 },
{ OPCODE_FRC, "FRC", 1, 1 },
{ OPCODE_IF, "IF", 1, 0 },
{ OPCODE_INT, "INT", 1, 1 },
{ OPCODE_KIL, "KIL", 1, 0 },
{ OPCODE_KIL_NV, "KIL", 0, 0 },
{ OPCODE_LG2, "LG2", 1, 1 },
@ -230,6 +229,7 @@ static const struct instruction_info InstInfo[MAX_OPCODE] = {
{ OPCODE_TXL, "TXL", 1, 1 },
{ OPCODE_TXP, "TXP", 1, 1 },
{ OPCODE_TXP_NV, "TXP", 1, 1 },
{ OPCODE_TRUNC, "TRUNC", 1, 1 },
{ OPCODE_UP2H, "UP2H", 1, 1 },
{ OPCODE_UP2US, "UP2US", 1, 1 },
{ OPCODE_UP4B, "UP4B", 1, 1 },

5
src/mesa/shader/prog_instruction.h
View file

@ -173,7 +173,6 @@ typedef enum prog_opcode {
OPCODE_FLR, /* X X 2 X X */
OPCODE_FRC, /* X X 2 X X */
OPCODE_IF, /* opt */
OPCODE_INT, /* X */
OPCODE_KIL, /* X */
OPCODE_KIL_NV, /* X X */
OPCODE_LG2, /* X X 2 X X */
@ -221,6 +220,7 @@ typedef enum prog_opcode {
OPCODE_TXL, /* 3 2 X */
OPCODE_TXP, /* X X */
OPCODE_TXP_NV, /* 3 X */
OPCODE_TRUNC, /* X */
OPCODE_UP2H, /* X */
OPCODE_UP2US, /* X */
OPCODE_UP4B, /* X */
@ -231,6 +231,9 @@ typedef enum prog_opcode {
} gl_inst_opcode;
/* temporary, just in case, remove soon */
#define OPCODE_INT OPCODE_TRUNC
/**
* Instruction source register.
*/

2
src/mesa/shader/slang/slang_ir.c
View file

@ -56,7 +56,7 @@ static const slang_ir_info IrInfo[] = {
/* unary ops */
{ IR_MOVE, "IR_MOVE", OPCODE_MOV, 4, 1 },
{ IR_I_TO_F, "IR_I_TO_F", OPCODE_MOV, 4, 1 }, /* int[4] to float[4] */
{ IR_F_TO_I, "IR_F_TO_I", OPCODE_INT, 4, 1 }, /* 4 floats to 4 ints */
{ IR_F_TO_I, "IR_F_TO_I", OPCODE_TRUNC, 4, 1 },
{ IR_EXP, "IR_EXP", OPCODE_EXP, 1, 1 },
{ IR_EXP2, "IR_EXP2", OPCODE_EX2, 1, 1 },
{ IR_LOG2, "IR_LOG2", OPCODE_LG2, 1, 1 },