diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py
index a262033322e..37e5d5eca08 100644
--- a/src/freedreno/common/freedreno_devices.py
+++ b/src/freedreno/common/freedreno_devices.py
@@ -1013,9 +1013,6 @@ a730_raw_magic_regs = [
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000],
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_B310, 0x00000000],
 
-        [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8120, 0x09510840],
-        [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8121, 0x00000a62],
-
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2,   0x00000000],
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2+1, 0x00000000],
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE4,   0x00000000],
@@ -1071,9 +1068,6 @@ a740_raw_magic_regs = [
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000],
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_B310, 0x00000000],
 
-        [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8120, 0x09510840],
-        [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8121, 0x00000a62],
-
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2,   0x00000000],
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2+1, 0x00000000],
         [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE4,   0x00000000],
@@ -1175,9 +1169,6 @@ add_gpus([
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_B310, 0x00000000],
 
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8120, 0x09510840],
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8121, 0x00000a62],
-
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2,   0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2+1, 0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE4,   0x00000000],
@@ -1250,9 +1241,6 @@ add_gpus([
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_B310, 0x00000000],
 
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8120, 0x09510840],
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8121, 0x00000a62],
-
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2,   0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2+1, 0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE4,   0x00000000],
@@ -1349,8 +1337,6 @@ add_gpus([
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB01, 0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_AB22, 0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_B310, 0x00000000],
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8120, 0x09510840],
-            [A6XXRegs.REG_A7XX_GRAS_UNKNOWN_8121, 0x00000a62],
 
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2,   0x00000000],
             [A6XXRegs.REG_A7XX_SP_UNKNOWN_0CE2+1, 0x00000000],
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 46cd19e35ed..196b46cda61 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -1278,9 +1278,8 @@ by a particular renderpass/blit.
 		<bitfield name="UNK3" pos="3"/>
 	</reg32>
 
-	<!-- Always written together and always equal 09510840 00000a62 -->
-	<reg32 offset="0x8120" name="GRAS_UNKNOWN_8120" variants="A7XX-" usage="cmd"/>
-	<reg32 offset="0x8121" name="GRAS_UNKNOWN_8121" variants="A7XX-" usage="cmd"/>
+	<doc>LUT used to convert quality buffer values to HW shading rate values. An array of 4-bit values.</doc>
+	<array offset="0x8120" name="GRAS_LRZ_QUALITY_LOOKUP_TABLE" variants="A7XX-" stride="1" length="2"/>
 
 	<!-- 0x8112-0x83ff invalid -->
 
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc
index 26fecd0de86..2b882a08e8d 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.cc
+++ b/src/freedreno/vulkan/tu_cmd_buffer.cc
@@ -24,6 +24,7 @@
 
 #include "common/freedreno_gpu_event.h"
 #include "common/freedreno_lrz.h"
+#include "common/freedreno_vrs.h"
 
 enum tu_cmd_buffer_status {
    TU_CMD_BUFFER_STATUS_IDLE = 0,
@@ -1712,6 +1713,13 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
       tu_cs_emit_write_reg(cs, magic_reg.reg, value);
    }
 
+   if (dev->physical_device->info->a6xx.has_attachment_shading_rate) {
+      tu_cs_emit_write_reg(cs, REG_A7XX_GRAS_LRZ_QUALITY_LOOKUP_TABLE(0),
+                           fd_gras_shading_rate_lut(0));
+      tu_cs_emit_write_reg(cs, REG_A7XX_GRAS_LRZ_QUALITY_LOOKUP_TABLE(1),
+                           fd_gras_shading_rate_lut(1));
+   }
+
    tu_cs_emit_write_reg(cs, REG_A6XX_RB_DBG_ECO_CNTL,
                         phys_dev->info->a6xx.magic.RB_DBG_ECO_CNTL);
    tu_cs_emit_write_reg(cs, REG_A6XX_SP_NC_MODE_CNTL_2, 0);