From 03346d62e7ab827d68fa013b426bf77b8d57adc8 Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Tue, 17 May 2022 08:18:26 -0700 Subject: [PATCH] radeonsi: r600: d3d12: st: Use NIR lowering for tg4 offset arrays instead of GLSL lowering MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I think I got all the drivers that need updating. This is only necessary in drivers that support GLSL 4.00 / GL_ARB_gpu_shader5 and have PIPE_CAP_TEXTURE_GATHER_OFFSETS = 0. v2: Don't (accidentally) condition tg4 offsets lowering on tex rect lowering. Noticed by Qiang. v3: Add missing bool() cast. v4: don't use designated initializers Fixes: 640f9098621 ("glsl: add _texture related sparse texture builtin functions") Closes: #6365 Tested-by: Qiang Yu Reviewed-by: Qiang Yu Reviewed-by: Marek Olšák Part-of: --- src/gallium/drivers/d3d12/d3d12_compiler.cpp | 1 + src/gallium/drivers/r600/sfn/sfn_nir.cpp | 1 + src/gallium/drivers/radeonsi/si_shader_nir.c | 1 + src/mesa/state_tracker/st_glsl_to_ir.cpp | 2 -- src/mesa/state_tracker/st_glsl_to_nir.cpp | 9 ++++++--- 5 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/d3d12/d3d12_compiler.cpp b/src/gallium/drivers/d3d12/d3d12_compiler.cpp index facd2f6640e..13d5808b250 100644 --- a/src/gallium/drivers/d3d12/d3d12_compiler.cpp +++ b/src/gallium/drivers/d3d12/d3d12_compiler.cpp @@ -1173,6 +1173,7 @@ select_shader_variant(struct d3d12_selection_context *sel_ctx, d3d12_shader_sele tex_options.saturate_r = key.tex_saturate_r; tex_options.saturate_t = key.tex_saturate_t; tex_options.lower_invalid_implicit_lod = true; + tex_options.lower_tg4_offsets = true; NIR_PASS_V(new_nir_variant, nir_lower_tex, &tex_options); } diff --git a/src/gallium/drivers/r600/sfn/sfn_nir.cpp b/src/gallium/drivers/r600/sfn/sfn_nir.cpp index 5609c03f290..792b7e8b542 100644 --- a/src/gallium/drivers/r600/sfn/sfn_nir.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_nir.cpp @@ -682,6 +682,7 @@ int r600_shader_from_nir(struct r600_context *rctx, lower_tex_options.lower_txp = ~0u; lower_tex_options.lower_txf_offset = true; lower_tex_options.lower_invalid_implicit_lod = true; + lower_tex_options.lower_tg4_offsets = true; NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options); NIR_PASS_V(sel->nir, r600_nir_lower_txl_txf_array_or_cube); diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c index 3ca2bf8adda..46c7e135955 100644 --- a/src/gallium/drivers/radeonsi/si_shader_nir.c +++ b/src/gallium/drivers/radeonsi/si_shader_nir.c @@ -251,6 +251,7 @@ static void si_lower_nir(struct si_screen *sscreen, struct nir_shader *nir) .lower_txp = ~0u, .lower_txs_cube_array = true, .lower_invalid_implicit_lod = true, + .lower_tg4_offsets = true, }; NIR_PASS_V(nir, nir_lower_tex, &lower_tex_options); diff --git a/src/mesa/state_tracker/st_glsl_to_ir.cpp b/src/mesa/state_tracker/st_glsl_to_ir.cpp index 79496f1e913..006f5de568e 100644 --- a/src/mesa/state_tracker/st_glsl_to_ir.cpp +++ b/src/mesa/state_tracker/st_glsl_to_ir.cpp @@ -94,8 +94,6 @@ link_shader(struct gl_context *ctx, struct gl_shader_program *prog) lower_packing_builtins(ir, lower_inst); } - if (!pscreen->get_param(pscreen, PIPE_CAP_TEXTURE_GATHER_OFFSETS)) - lower_offset_arrays(ir); do_mat_op_to_vec(ir); if (stage == MESA_SHADER_FRAGMENT && pscreen->get_param(pscreen, PIPE_CAP_FBFETCH)) diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp b/src/mesa/state_tracker/st_glsl_to_nir.cpp index 57ea9f67c0f..17f0632093e 100644 --- a/src/mesa/state_tracker/st_glsl_to_nir.cpp +++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp @@ -1029,10 +1029,13 @@ st_finalize_nir(struct st_context *st, struct gl_program *prog, NIR_PASS_V(nir, nir_split_var_copies); NIR_PASS_V(nir, nir_lower_var_copies); - if (st->lower_rect_tex) { - struct nir_lower_tex_options opts = { 0 }; + const bool lower_tg4_offsets = + !st->screen->get_param(screen, PIPE_CAP_TEXTURE_GATHER_OFFSETS); - opts.lower_rect = true; + if (st->lower_rect_tex || lower_tg4_offsets) { + struct nir_lower_tex_options opts = {0}; + opts.lower_rect = !!st->lower_rect_tex; + opts.lower_tg4_offsets = lower_tg4_offsets; NIR_PASS_V(nir, nir_lower_tex, &opts); }