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radeonsi: move enabled_mask out of si_descriptors
This mask is irrelevant for the generic descriptor set handling, and having it outside simplifies subsequent changes slightly. Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Nicolai Hähnle
parent
d1e141a661
commit
031b57bc2f
4 changed files with 34 additions and 30 deletions
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@ -415,7 +415,7 @@ si_decompress_image_color_textures(struct si_context *sctx,
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static void si_check_render_feedback_textures(struct si_context *sctx,
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struct si_textures_info *textures)
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{
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uint32_t mask = textures->views.desc.enabled_mask;
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uint32_t mask = textures->views.enabled_mask;
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while (mask) {
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const struct pipe_sampler_view *view;
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@ -458,7 +458,7 @@ static void si_check_render_feedback_textures(struct si_context *sctx,
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static void si_check_render_feedback_images(struct si_context *sctx,
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struct si_images_info *images)
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{
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uint32_t mask = images->desc.enabled_mask;
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uint32_t mask = images->enabled_mask;
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while (mask) {
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const struct pipe_image_view *view;
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@ -106,7 +106,7 @@ static void si_init_descriptors(struct si_descriptors *desc,
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{
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int i;
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assert(num_elements <= sizeof(desc->enabled_mask)*8);
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assert(num_elements <= sizeof(desc->dirty_mask)*8);
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desc->list = CALLOC(num_elements, element_dw_size * 4);
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desc->element_dw_size = element_dw_size;
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@ -277,7 +277,7 @@ static void si_sampler_view_add_buffer(struct si_context *sctx,
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static void si_sampler_views_begin_new_cs(struct si_context *sctx,
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struct si_sampler_views *views)
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{
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unsigned mask = views->desc.enabled_mask;
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unsigned mask = views->enabled_mask;
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/* Add buffers to the CS. */
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while (mask) {
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@ -369,13 +369,13 @@ static void si_set_sampler_view(struct si_context *sctx,
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views->sampler_states[slot], 4*4);
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}
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views->desc.enabled_mask |= 1u << slot;
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views->enabled_mask |= 1u << slot;
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} else {
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pipe_sampler_view_reference(&views->views[slot], NULL);
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memcpy(views->desc.list + slot*16, null_texture_descriptor, 8*4);
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/* Only clear the lower dwords of FMASK. */
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memcpy(views->desc.list + slot*16 + 8, null_texture_descriptor, 4*4);
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views->desc.enabled_mask &= ~(1u << slot);
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views->enabled_mask &= ~(1u << slot);
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}
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views->desc.dirty_mask |= 1u << slot;
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@ -439,7 +439,7 @@ static void si_set_sampler_views(struct pipe_context *ctx,
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static void
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si_samplers_update_compressed_colortex_mask(struct si_textures_info *samplers)
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{
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unsigned mask = samplers->views.desc.enabled_mask;
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unsigned mask = samplers->views.enabled_mask;
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while (mask) {
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int i = u_bit_scan(&mask);
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@ -476,7 +476,7 @@ si_release_image_views(struct si_images_info *images)
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static void
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si_image_views_begin_new_cs(struct si_context *sctx, struct si_images_info *images)
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{
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uint mask = images->desc.enabled_mask;
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uint mask = images->enabled_mask;
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/* Add buffers to the CS. */
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while (mask) {
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@ -502,12 +502,12 @@ si_image_views_begin_new_cs(struct si_context *sctx, struct si_images_info *imag
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static void
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si_disable_shader_image(struct si_images_info *images, unsigned slot)
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{
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if (images->desc.enabled_mask & (1u << slot)) {
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if (images->enabled_mask & (1u << slot)) {
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pipe_resource_reference(&images->views[slot].resource, NULL);
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images->compressed_colortex_mask &= ~(1 << slot);
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memcpy(images->desc.list + slot*8, null_image_descriptor, 8*4);
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images->desc.enabled_mask &= ~(1u << slot);
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images->enabled_mask &= ~(1u << slot);
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images->desc.dirty_mask |= 1u << slot;
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}
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}
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@ -613,7 +613,7 @@ static void si_set_shader_image(struct si_context *ctx,
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false, desc);
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}
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images->desc.enabled_mask |= 1u << slot;
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images->enabled_mask |= 1u << slot;
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images->desc.dirty_mask |= 1u << slot;
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}
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@ -645,7 +645,7 @@ si_set_shader_images(struct pipe_context *pipe, unsigned shader,
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static void
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si_images_update_compressed_colortex_mask(struct si_images_info *images)
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{
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unsigned mask = images->desc.enabled_mask;
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unsigned mask = images->enabled_mask;
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while (mask) {
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int i = u_bit_scan(&mask);
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@ -732,7 +732,7 @@ static void si_release_buffer_resources(struct si_buffer_resources *buffers)
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static void si_buffer_resources_begin_new_cs(struct si_context *sctx,
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struct si_buffer_resources *buffers)
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{
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unsigned mask = buffers->desc.enabled_mask;
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unsigned mask = buffers->enabled_mask;
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/* Add buffers to the CS. */
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while (mask) {
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@ -929,11 +929,11 @@ void si_set_constant_buffer(struct si_context *sctx,
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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(struct r600_resource*)buffer,
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buffers->shader_usage, buffers->priority);
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buffers->desc.enabled_mask |= 1u << slot;
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buffers->enabled_mask |= 1u << slot;
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} else {
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/* Clear the descriptor. */
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memset(buffers->desc.list + slot*4, 0, sizeof(uint32_t) * 4);
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buffers->desc.enabled_mask &= ~(1u << slot);
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buffers->enabled_mask &= ~(1u << slot);
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}
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buffers->desc.dirty_mask |= 1u << slot;
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@ -973,7 +973,7 @@ static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
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if (!sbuffer || !sbuffer->buffer) {
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pipe_resource_reference(&buffers->buffers[slot], NULL);
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memset(desc, 0, sizeof(uint32_t) * 4);
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buffers->desc.enabled_mask &= ~(1u << slot);
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buffers->enabled_mask &= ~(1u << slot);
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buffers->desc.dirty_mask |= 1u << slot;
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continue;
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}
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@ -995,7 +995,7 @@ static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
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pipe_resource_reference(&buffers->buffers[slot], &buf->b.b);
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buf,
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buffers->shader_usage, buffers->priority);
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buffers->desc.enabled_mask |= 1u << slot;
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buffers->enabled_mask |= 1u << slot;
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buffers->desc.dirty_mask |= 1u << slot;
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}
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}
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@ -1082,11 +1082,11 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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(struct r600_resource*)buffer,
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buffers->shader_usage, buffers->priority);
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buffers->desc.enabled_mask |= 1u << slot;
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buffers->enabled_mask |= 1u << slot;
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} else {
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/* Clear the descriptor. */
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memset(buffers->desc.list + slot*4, 0, sizeof(uint32_t) * 4);
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buffers->desc.enabled_mask &= ~(1u << slot);
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buffers->enabled_mask &= ~(1u << slot);
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}
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buffers->desc.dirty_mask |= 1u << slot;
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@ -1179,14 +1179,14 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
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radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
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(struct r600_resource*)buffer,
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buffers->shader_usage, buffers->priority);
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buffers->desc.enabled_mask |= 1u << bufidx;
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buffers->enabled_mask |= 1u << bufidx;
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} else {
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/* Clear the descriptor and unset the resource. */
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memset(buffers->desc.list + bufidx*4, 0,
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sizeof(uint32_t) * 4);
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pipe_resource_reference(&buffers->buffers[bufidx],
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NULL);
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buffers->desc.enabled_mask &= ~(1u << bufidx);
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buffers->enabled_mask &= ~(1u << bufidx);
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}
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buffers->desc.dirty_mask |= 1u << bufidx;
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}
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@ -1195,7 +1195,7 @@ static void si_set_streamout_targets(struct pipe_context *ctx,
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/* Clear the descriptor and unset the resource. */
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memset(buffers->desc.list + bufidx*4, 0, sizeof(uint32_t) * 4);
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pipe_resource_reference(&buffers->buffers[bufidx], NULL);
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buffers->desc.enabled_mask &= ~(1u << bufidx);
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buffers->enabled_mask &= ~(1u << bufidx);
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buffers->desc.dirty_mask |= 1u << bufidx;
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}
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}
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@ -1261,7 +1261,7 @@ static void si_reset_buffer_resources(struct si_context *sctx,
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struct pipe_resource *buf,
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uint64_t old_va)
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{
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unsigned mask = buffers->desc.enabled_mask;
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unsigned mask = buffers->enabled_mask;
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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@ -1361,7 +1361,7 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
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/* Texture buffers - update bindings. */
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for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
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struct si_sampler_views *views = &sctx->samplers[shader].views;
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unsigned mask = views->desc.enabled_mask;
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unsigned mask = views->enabled_mask;
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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@ -1382,7 +1382,7 @@ static void si_invalidate_buffer(struct pipe_context *ctx, struct pipe_resource
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/* Shader images */
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for (shader = 0; shader < SI_NUM_SHADERS; ++shader) {
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struct si_images_info *images = &sctx->images[shader];
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unsigned mask = images->desc.enabled_mask;
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unsigned mask = images->enabled_mask;
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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@ -1416,7 +1416,7 @@ void si_update_all_texture_descriptors(struct si_context *sctx)
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unsigned mask;
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/* Images. */
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mask = images->desc.enabled_mask;
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mask = images->enabled_mask;
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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struct pipe_image_view *view = &images->views[i];
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@ -1429,7 +1429,7 @@ void si_update_all_texture_descriptors(struct si_context *sctx)
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}
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/* Sampler views. */
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mask = samplers->desc.enabled_mask;
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mask = samplers->enabled_mask;
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while (mask) {
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unsigned i = u_bit_scan(&mask);
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struct pipe_sampler_view *view = samplers->views[i];
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@ -148,6 +148,7 @@ struct si_images_info {
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struct si_descriptors desc;
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struct pipe_image_view views[SI_NUM_IMAGES];
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uint32_t compressed_colortex_mask;
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unsigned enabled_mask;
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};
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struct si_framebuffer {
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@ -199,9 +199,6 @@ struct si_descriptors {
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/* Offset in CE RAM */
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unsigned ce_offset;
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/* The i-th bit is set if that element is enabled (non-NULL resource). */
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unsigned enabled_mask;
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/* elements of the list that are changed and need to be uploaded */
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unsigned dirty_mask;
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@ -220,6 +217,9 @@ struct si_sampler_views {
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struct si_descriptors desc;
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struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
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void *sampler_states[SI_NUM_SAMPLERS];
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/* The i-th bit is set if that element is enabled (non-NULL resource). */
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unsigned enabled_mask;
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};
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struct si_buffer_resources {
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@ -227,6 +227,9 @@ struct si_buffer_resources {
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enum radeon_bo_usage shader_usage; /* READ, WRITE, or READWRITE */
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enum radeon_bo_priority priority;
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struct pipe_resource **buffers; /* this has num_buffers elements */
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/* The i-th bit is set if that element is enabled (non-NULL resource). */
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unsigned enabled_mask;
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};
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#define si_pm4_block_idx(member) \
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