From 02d7f5e4ff1a93d149778d8b40f327cccbb412ee Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Tapani=20P=C3=A4lli?= <tapani.palli@intel.com>
Date: Thu, 18 Jan 2024 07:21:31 +0200
Subject: [PATCH] anv: expand pre-hiz data cache flush to gfx >= 125
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Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27132>
---
 src/intel/vulkan/anv_blorp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 24593dba6fc..ce5c63e7c31 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1884,7 +1884,7 @@ anv_fast_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
        * experiment shows that flusing the data cache helps to resolve the
        * corruption.
        */
-      unsigned wa_flush = intel_device_info_is_dg2(cmd_buffer->device->info) ?
+      unsigned wa_flush = cmd_buffer->device->info->verx10 >= 125 ?
                           ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0;
       anv_add_pending_pipe_bits(cmd_buffer,
                                 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |