From 02d7c8f9d3787209d7227c440e5663745eb27f8c Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Mon, 5 May 2025 12:55:03 +0200 Subject: [PATCH] spirv: Update the JSON and headers Signed-off-by: Samuel Pitoiset Part-of: --- src/compiler/spirv/spirv.core.grammar.json | 108 ++++++++++++++++++++- src/compiler/spirv/spirv.h | 31 ++++++ 2 files changed, 134 insertions(+), 5 deletions(-) diff --git a/src/compiler/spirv/spirv.core.grammar.json b/src/compiler/spirv/spirv.core.grammar.json index f3b3cbcf1fa..8288f42aa19 100644 --- a/src/compiler/spirv/spirv.core.grammar.json +++ b/src/compiler/spirv/spirv.core.grammar.json @@ -6300,8 +6300,8 @@ "operands" : [ { "kind" : "IdResult" } ], - "capabilities" : [ "RayTracingNV" , "RayTracingKHR", "RayQueryKHR" ], - "extensions" : [ "SPV_NV_ray_tracing" , "SPV_KHR_ray_tracing", "SPV_KHR_ray_query" ], + "capabilities" : [ "RayTracingNV" , "RayTracingKHR", "RayQueryKHR", "DisplacementMicromapNV" ], + "extensions" : [ "SPV_NV_ray_tracing" , "SPV_KHR_ray_tracing", "SPV_KHR_ray_query", "SPV_NV_displacement_micromap" ], "version" : "None" }, { @@ -9999,7 +9999,6 @@ "operands" : [ { "kind" : "IdResultType" }, { "kind" : "IdResult" }, - { "kind" : "IdRef", "name" : "'Result'" }, { "kind" : "IdRef", "name" : "'Input'" } ], "capabilities" : [ "FPGARegINTEL" ], @@ -10639,6 +10638,21 @@ "capabilities" : [ "SubgroupMatrixMultiplyAccumulateINTEL" ], "version" : "None" }, + { + "opname" : "OpBitwiseFunctionINTEL", + "class" : "Bit", + "opcode" : 6242, + "operands" : [ + { "kind" : "IdResultType" }, + { "kind" : "IdResult" }, + { "kind" : "IdRef", "name" : "'A'" }, + { "kind" : "IdRef", "name" : "'B'" }, + { "kind" : "IdRef", "name" : "'C'" }, + { "kind" : "IdRef", "name" : "'LUTIndex'" } + ], + "capabilities" : [ "TernaryBitwiseFunctionINTEL" ], + "version" : "None" + }, { "opname" : "OpGroupIMulKHR", "class" : "Group", @@ -12134,6 +12148,23 @@ ], "version" : "1.4" }, + { + "enumerant" : "NonCoherentTileAttachmentReadQCOM", + "value" : 4489, + "capabilities" : [ "TileShadingQCOM" ], + "version" : "None" + }, + { + "enumerant" : "TileShadingRateQCOM", + "value" : 4490, + "parameters" : [ + { "kind" : "LiteralInteger", "name" : "'x rate'" }, + { "kind" : "LiteralInteger", "name" : "'y rate'" }, + { "kind" : "LiteralInteger", "name" : "'z rate'" } + ], + "capabilities" : [ "TileShadingQCOM" ], + "version": "None" + }, { "enumerant": "EarlyAndLateFragmentTestsAMD", "value": 5017, @@ -12611,6 +12642,12 @@ "capabilities" : [ "TileImageColorReadAccessEXT" ], "version" : "None" }, + { + "enumerant" : "TileAttachmentQCOM", + "value" : 4491, + "capabilities" : [ "TileShadingQCOM" ], + "version" : "None" + }, { "enumerant" : "NodePayloadAMDX", "value" : 5068, @@ -13265,6 +13302,11 @@ "value" : 16, "version": "1.0" }, + { + "enumerant" : "UnormInt10X6EXT", + "value" : 17, + "version": "1.0" + }, { "enumerant" : "UnsignedIntRaw10EXT", "value" : 19, @@ -13279,6 +13321,31 @@ "enumerant" : "UnormInt2_101010EXT", "value" : 21, "version": "1.0" + }, + { + "enumerant" : "UnsignedInt10X6EXT", + "value" : 22, + "version": "1.0" + }, + { + "enumerant" : "UnsignedInt12X4EXT", + "value" : 23, + "version": "1.0" + }, + { + "enumerant" : "UnsignedInt14X2EXT", + "value" : 24, + "version": "1.0" + }, + { + "enumerant" : "UnormInt12X4EXT", + "value" : 25, + "version": "1.0" + }, + { + "enumerant" : "UnormInt14X2EXT", + "value" : 26, + "version": "1.0" } ] }, @@ -14071,8 +14138,8 @@ { "enumerant" : "PerTaskNV", "value" : 5273, - "capabilities" : [ "MeshShadingNV", "MeshShadingEXT" ], - "extensions" : [ "SPV_NV_mesh_shader", "SPV_EXT_mesh_shader" ], + "capabilities" : [ "MeshShadingNV" ], + "extensions" : [ "SPV_NV_mesh_shader" ], "version" : "None" }, { @@ -15049,6 +15116,24 @@ "extensions" : [ "SPV_KHR_fragment_shading_rate" ], "version" : "None" }, + { + "enumerant" : "TileOffsetQCOM", + "value" : 4492, + "capabilities" : [ "TileShadingQCOM" ], + "version" : "None" + }, + { + "enumerant" : "TileDimensionQCOM", + "value" : 4493, + "capabilities" : [ "TileShadingQCOM" ], + "version" : "None" + }, + { + "enumerant" : "TileApronSizeQCOM", + "value" : 4494, + "capabilities" : [ "TileShadingQCOM" ], + "version" : "None" + }, { "enumerant" : "BaryCoordNoPerspAMD", "value" : 4992, @@ -16285,6 +16370,13 @@ "extensions" : [ "SPV_QCOM_image_processing" ], "version" : "None" }, + { + "enumerant" : "TileShadingQCOM", + "value" : 4495, + "capabilities" : [ "Shader" ], + "extensions" : [ "SPV_QCOM_tile_shading" ], + "version" : "None" + }, { "enumerant" : "TextureBlockMatch2QCOM", "value" : 4498, @@ -17246,6 +17338,12 @@ "extensions": [ "SPV_INTEL_subgroup_matrix_multiply_accumulate" ], "version" : "None" }, + { + "enumerant" : "TernaryBitwiseFunctionINTEL", + "value" : 6241, + "extensions" : [ "SPV_INTEL_ternary_bitwise_function"], + "version" : "None" + }, { "enumerant" : "GroupUniformArithmeticKHR", "value" : 6400, diff --git a/src/compiler/spirv/spirv.h b/src/compiler/spirv/spirv.h index bc87ffa6711..d8df1b33d83 100644 --- a/src/compiler/spirv/spirv.h +++ b/src/compiler/spirv/spirv.h @@ -176,6 +176,8 @@ typedef enum SpvExecutionMode_ { SpvExecutionModeSignedZeroInfNanPreserve = 4461, SpvExecutionModeRoundingModeRTE = 4462, SpvExecutionModeRoundingModeRTZ = 4463, + SpvExecutionModeNonCoherentTileAttachmentReadQCOM = 4489, + SpvExecutionModeTileShadingRateQCOM = 4490, SpvExecutionModeEarlyAndLateFragmentTestsAMD = 5017, SpvExecutionModeStencilRefReplacingEXT = 5027, SpvExecutionModeCoalescingAMDX = 5069, @@ -245,6 +247,7 @@ typedef enum SpvStorageClass_ { SpvStorageClassImage = 11, SpvStorageClassStorageBuffer = 12, SpvStorageClassTileImageEXT = 4172, + SpvStorageClassTileAttachmentQCOM = 4491, SpvStorageClassNodePayloadAMDX = 5068, SpvStorageClassCallableDataKHR = 5328, SpvStorageClassCallableDataNV = 5328, @@ -383,9 +386,15 @@ typedef enum SpvImageChannelDataType_ { SpvImageChannelDataTypeFloat = 14, SpvImageChannelDataTypeUnormInt24 = 15, SpvImageChannelDataTypeUnormInt101010_2 = 16, + SpvImageChannelDataTypeUnormInt10X6EXT = 17, SpvImageChannelDataTypeUnsignedIntRaw10EXT = 19, SpvImageChannelDataTypeUnsignedIntRaw12EXT = 20, SpvImageChannelDataTypeUnormInt2_101010EXT = 21, + SpvImageChannelDataTypeUnsignedInt10X6EXT = 22, + SpvImageChannelDataTypeUnsignedInt12X4EXT = 23, + SpvImageChannelDataTypeUnsignedInt14X2EXT = 24, + SpvImageChannelDataTypeUnormInt12X4EXT = 25, + SpvImageChannelDataTypeUnormInt14X2EXT = 26, SpvImageChannelDataTypeMax = 0x7fffffff, } SpvImageChannelDataType; @@ -717,6 +726,9 @@ typedef enum SpvBuiltIn_ { SpvBuiltInDeviceIndex = 4438, SpvBuiltInViewIndex = 4440, SpvBuiltInShadingRateKHR = 4444, + SpvBuiltInTileOffsetQCOM = 4492, + SpvBuiltInTileDimensionQCOM = 4493, + SpvBuiltInTileApronSizeQCOM = 4494, SpvBuiltInBaryCoordNoPerspAMD = 4992, SpvBuiltInBaryCoordNoPerspCentroidAMD = 4993, SpvBuiltInBaryCoordNoPerspSampleAMD = 4994, @@ -1103,6 +1115,7 @@ typedef enum SpvCapability_ { SpvCapabilityTextureSampleWeightedQCOM = 4484, SpvCapabilityTextureBoxFilterQCOM = 4485, SpvCapabilityTextureBlockMatchQCOM = 4486, + SpvCapabilityTileShadingQCOM = 4495, SpvCapabilityTextureBlockMatch2QCOM = 4498, SpvCapabilityFloat16ImageAMD = 5008, SpvCapabilityImageGatherBiasLodAMD = 5009, @@ -1275,6 +1288,7 @@ typedef enum SpvCapability_ { SpvCapabilitySubgroup2DBlockTransformINTEL = 6229, SpvCapabilitySubgroup2DBlockTransposeINTEL = 6230, SpvCapabilitySubgroupMatrixMultiplyAccumulateINTEL = 6236, + SpvCapabilityTernaryBitwiseFunctionINTEL = 6241, SpvCapabilityGroupUniformArithmeticKHR = 6400, SpvCapabilityTensorFloat32RoundingINTEL = 6425, SpvCapabilityMaskedGatherScatterINTEL = 6427, @@ -2366,6 +2380,7 @@ typedef enum SpvOp_ { SpvOpSubgroup2DBlockPrefetchINTEL = 6234, SpvOpSubgroup2DBlockStoreINTEL = 6235, SpvOpSubgroupMatrixMultiplyAccumulateINTEL = 6237, + SpvOpBitwiseFunctionINTEL = 6242, SpvOpGroupIMulKHR = 6401, SpvOpGroupFMulKHR = 6402, SpvOpGroupBitwiseAndKHR = 6403, @@ -3170,6 +3185,7 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy case SpvOpSubgroup2DBlockPrefetchINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpSubgroup2DBlockStoreINTEL: *hasResult = false; *hasResultType = false; break; case SpvOpSubgroupMatrixMultiplyAccumulateINTEL: *hasResult = true; *hasResultType = true; break; + case SpvOpBitwiseFunctionINTEL: *hasResult = true; *hasResultType = true; break; case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; case SpvOpGroupFMulKHR: *hasResult = true; *hasResultType = true; break; case SpvOpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break; @@ -3296,6 +3312,8 @@ inline const char* SpvExecutionModeToString(SpvExecutionMode value) { case SpvExecutionModeSignedZeroInfNanPreserve: return "SignedZeroInfNanPreserve"; case SpvExecutionModeRoundingModeRTE: return "RoundingModeRTE"; case SpvExecutionModeRoundingModeRTZ: return "RoundingModeRTZ"; + case SpvExecutionModeNonCoherentTileAttachmentReadQCOM: return "NonCoherentTileAttachmentReadQCOM"; + case SpvExecutionModeTileShadingRateQCOM: return "TileShadingRateQCOM"; case SpvExecutionModeEarlyAndLateFragmentTestsAMD: return "EarlyAndLateFragmentTestsAMD"; case SpvExecutionModeStencilRefReplacingEXT: return "StencilRefReplacingEXT"; case SpvExecutionModeCoalescingAMDX: return "CoalescingAMDX"; @@ -3362,6 +3380,7 @@ inline const char* SpvStorageClassToString(SpvStorageClass value) { case SpvStorageClassImage: return "Image"; case SpvStorageClassStorageBuffer: return "StorageBuffer"; case SpvStorageClassTileImageEXT: return "TileImageEXT"; + case SpvStorageClassTileAttachmentQCOM: return "TileAttachmentQCOM"; case SpvStorageClassNodePayloadAMDX: return "NodePayloadAMDX"; case SpvStorageClassCallableDataKHR: return "CallableDataKHR"; case SpvStorageClassIncomingCallableDataKHR: return "IncomingCallableDataKHR"; @@ -3505,9 +3524,15 @@ inline const char* SpvImageChannelDataTypeToString(SpvImageChannelDataType value case SpvImageChannelDataTypeFloat: return "Float"; case SpvImageChannelDataTypeUnormInt24: return "UnormInt24"; case SpvImageChannelDataTypeUnormInt101010_2: return "UnormInt101010_2"; + case SpvImageChannelDataTypeUnormInt10X6EXT: return "UnormInt10X6EXT"; case SpvImageChannelDataTypeUnsignedIntRaw10EXT: return "UnsignedIntRaw10EXT"; case SpvImageChannelDataTypeUnsignedIntRaw12EXT: return "UnsignedIntRaw12EXT"; case SpvImageChannelDataTypeUnormInt2_101010EXT: return "UnormInt2_101010EXT"; + case SpvImageChannelDataTypeUnsignedInt10X6EXT: return "UnsignedInt10X6EXT"; + case SpvImageChannelDataTypeUnsignedInt12X4EXT: return "UnsignedInt12X4EXT"; + case SpvImageChannelDataTypeUnsignedInt14X2EXT: return "UnsignedInt14X2EXT"; + case SpvImageChannelDataTypeUnormInt12X4EXT: return "UnormInt12X4EXT"; + case SpvImageChannelDataTypeUnormInt14X2EXT: return "UnormInt14X2EXT"; default: return "Unknown"; } } @@ -3763,6 +3788,9 @@ inline const char* SpvBuiltInToString(SpvBuiltIn value) { case SpvBuiltInDeviceIndex: return "DeviceIndex"; case SpvBuiltInViewIndex: return "ViewIndex"; case SpvBuiltInShadingRateKHR: return "ShadingRateKHR"; + case SpvBuiltInTileOffsetQCOM: return "TileOffsetQCOM"; + case SpvBuiltInTileDimensionQCOM: return "TileDimensionQCOM"; + case SpvBuiltInTileApronSizeQCOM: return "TileApronSizeQCOM"; case SpvBuiltInBaryCoordNoPerspAMD: return "BaryCoordNoPerspAMD"; case SpvBuiltInBaryCoordNoPerspCentroidAMD: return "BaryCoordNoPerspCentroidAMD"; case SpvBuiltInBaryCoordNoPerspSampleAMD: return "BaryCoordNoPerspSampleAMD"; @@ -3977,6 +4005,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) { case SpvCapabilityTextureSampleWeightedQCOM: return "TextureSampleWeightedQCOM"; case SpvCapabilityTextureBoxFilterQCOM: return "TextureBoxFilterQCOM"; case SpvCapabilityTextureBlockMatchQCOM: return "TextureBlockMatchQCOM"; + case SpvCapabilityTileShadingQCOM: return "TileShadingQCOM"; case SpvCapabilityTextureBlockMatch2QCOM: return "TextureBlockMatch2QCOM"; case SpvCapabilityFloat16ImageAMD: return "Float16ImageAMD"; case SpvCapabilityImageGatherBiasLodAMD: return "ImageGatherBiasLodAMD"; @@ -4123,6 +4152,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) { case SpvCapabilitySubgroup2DBlockTransformINTEL: return "Subgroup2DBlockTransformINTEL"; case SpvCapabilitySubgroup2DBlockTransposeINTEL: return "Subgroup2DBlockTransposeINTEL"; case SpvCapabilitySubgroupMatrixMultiplyAccumulateINTEL: return "SubgroupMatrixMultiplyAccumulateINTEL"; + case SpvCapabilityTernaryBitwiseFunctionINTEL: return "TernaryBitwiseFunctionINTEL"; case SpvCapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR"; case SpvCapabilityTensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL"; case SpvCapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL"; @@ -5102,6 +5132,7 @@ inline const char* SpvOpToString(SpvOp value) { case SpvOpSubgroup2DBlockPrefetchINTEL: return "OpSubgroup2DBlockPrefetchINTEL"; case SpvOpSubgroup2DBlockStoreINTEL: return "OpSubgroup2DBlockStoreINTEL"; case SpvOpSubgroupMatrixMultiplyAccumulateINTEL: return "OpSubgroupMatrixMultiplyAccumulateINTEL"; + case SpvOpBitwiseFunctionINTEL: return "OpBitwiseFunctionINTEL"; case SpvOpGroupIMulKHR: return "OpGroupIMulKHR"; case SpvOpGroupFMulKHR: return "OpGroupFMulKHR"; case SpvOpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR";