diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index ea7f3c69867..a93f4b27415 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -200,226 +200,6 @@ fd_query_memory_info(struct pipe_screen *pscreen, info->avail_device_memory = mem; } -static int -fd_screen_get_shader_param(struct pipe_screen *pscreen, - enum pipe_shader_type shader, - enum pipe_shader_cap param) -{ - struct fd_screen *screen = fd_screen(pscreen); - - switch (shader) { - case PIPE_SHADER_FRAGMENT: - case PIPE_SHADER_VERTEX: - break; - case PIPE_SHADER_TESS_CTRL: - case PIPE_SHADER_TESS_EVAL: - case PIPE_SHADER_GEOMETRY: - if (is_a6xx(screen)) - break; - return 0; - case PIPE_SHADER_COMPUTE: - if (has_compute(screen)) - break; - return 0; - case PIPE_SHADER_TASK: - case PIPE_SHADER_MESH: - return 0; - default: - mesa_loge("unknown shader type %d", shader); - return 0; - } - - /* this is probably not totally correct.. but it's a start: */ - switch (param) { - case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: - case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: - case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: - case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: - return 16384; - case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: - return 8; /* XXX */ - case PIPE_SHADER_CAP_MAX_INPUTS: - if (shader == PIPE_SHADER_GEOMETRY && is_a6xx(screen)) - return 16; - return is_a6xx(screen) ? - (screen->info->a6xx.vs_max_inputs_count) : 16; - case PIPE_SHADER_CAP_MAX_OUTPUTS: - return is_a6xx(screen) ? 32 : 16; - case PIPE_SHADER_CAP_MAX_TEMPS: - return 64; /* Max native temporaries. */ - case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE: - /* NOTE: seems to be limit for a3xx is actually 512 but - * split between VS and FS. Use lower limit of 256 to - * avoid getting into impossible situations: - */ - return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) || - is_a6xx(screen)) - ? 4096 - : 64) * - sizeof(float[4]); - case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: - return is_ir3(screen) ? 16 : 1; - case PIPE_SHADER_CAP_CONT_SUPPORTED: - return 1; - case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: - case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: - /* a2xx compiler doesn't handle indirect: */ - return is_ir3(screen) ? 1 : 0; - case PIPE_SHADER_CAP_SUBROUTINES: - case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: - case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: - case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: - return 0; - case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: - return 1; - case PIPE_SHADER_CAP_INTEGERS: - return is_ir3(screen) ? 1 : 0; - case PIPE_SHADER_CAP_INT64_ATOMICS: - case PIPE_SHADER_CAP_FP16_DERIVATIVES: - case PIPE_SHADER_CAP_FP16_CONST_BUFFERS: - case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS: - return 0; - case PIPE_SHADER_CAP_INT16: - case PIPE_SHADER_CAP_FP16: - return ( - (is_a5xx(screen) || is_a6xx(screen)) && - (shader == PIPE_SHADER_COMPUTE || shader == PIPE_SHADER_FRAGMENT) && - !FD_DBG(NOFP16)); - case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: - case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: - return 16; - case PIPE_SHADER_CAP_SUPPORTED_IRS: - return (1 << PIPE_SHADER_IR_NIR) | - /* tgsi_to_nir doesn't support all stages: */ - COND((shader == PIPE_SHADER_VERTEX) || - (shader == PIPE_SHADER_FRAGMENT) || - (shader == PIPE_SHADER_COMPUTE), - (1 << PIPE_SHADER_IR_TGSI)); - case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: - case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: - if (is_a6xx(screen)) { - if (param == PIPE_SHADER_CAP_MAX_SHADER_BUFFERS) { - return IR3_BINDLESS_SSBO_COUNT; - } else { - return IR3_BINDLESS_IMAGE_COUNT; - } - } else if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) { - /* a5xx (and a4xx for that matter) has one state-block - * for compute-shader SSBO's and another that is shared - * by VS/HS/DS/GS/FS.. so to simplify things for now - * just advertise SSBOs for FS and CS. We could possibly - * do what blob does, and partition the space for - * VS/HS/DS/GS/FS. The blob advertises: - * - * GL_MAX_VERTEX_SHADER_STORAGE_BLOCKS: 4 - * GL_MAX_GEOMETRY_SHADER_STORAGE_BLOCKS: 4 - * GL_MAX_TESS_CONTROL_SHADER_STORAGE_BLOCKS: 4 - * GL_MAX_TESS_EVALUATION_SHADER_STORAGE_BLOCKS: 4 - * GL_MAX_FRAGMENT_SHADER_STORAGE_BLOCKS: 4 - * GL_MAX_COMPUTE_SHADER_STORAGE_BLOCKS: 24 - * GL_MAX_COMBINED_SHADER_STORAGE_BLOCKS: 24 - * - * I think that way we could avoid having to patch shaders - * for actual SSBO indexes by using a static partitioning. - * - * Note same state block is used for images and buffers, - * but images also need texture state for read access - * (isam/isam.3d) - */ - switch (shader) { - case PIPE_SHADER_FRAGMENT: - case PIPE_SHADER_COMPUTE: - return 24; - default: - return 0; - } - } - return 0; - } - mesa_loge("unknown shader param %d", param); - return 0; -} - -/* TODO depending on how much the limits differ for a3xx/a4xx, maybe move this - * into per-generation backend? - */ -static int -fd_get_compute_param(struct pipe_screen *pscreen, - enum pipe_compute_cap param, void *ret) -{ - struct fd_screen *screen = fd_screen(pscreen); - const char *const ir = "ir3"; - - if (!has_compute(screen)) - return 0; - - struct ir3_compiler *compiler = screen->compiler; - -#define RET(x) \ - do { \ - if (ret) \ - memcpy(ret, x, sizeof(x)); \ - return sizeof(x); \ - } while (0) - - switch (param) { - case PIPE_COMPUTE_CAP_ADDRESS_BITS: - if (screen->gen >= 5) - RET((uint32_t[]){64}); - RET((uint32_t[]){32}); - - case PIPE_COMPUTE_CAP_IR_TARGET: - if (ret) - sprintf(ret, "%s", ir); - return strlen(ir) * sizeof(char); - - case PIPE_COMPUTE_CAP_GRID_DIMENSION: - RET((uint64_t[]){3}); - - case PIPE_COMPUTE_CAP_MAX_GRID_SIZE: - RET(((uint64_t[]){65535, 65535, 65535})); - - case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE: - RET(((uint64_t[]){1024, 1024, 64})); - - case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK: - RET((uint64_t[]){1024}); - - case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: - RET((uint64_t[]){screen->ram_size}); - - case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: - RET((uint64_t[]){screen->info->cs_shared_mem_size}); - - case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: - case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: - RET((uint64_t[]){4096}); - - case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE: - RET((uint64_t[]){screen->ram_size}); - - case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY: - RET((uint32_t[]){screen->max_freq / 1000000}); - - case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS: - RET((uint32_t[]){9999}); // TODO - - case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED: - RET((uint32_t[]){1}); - - case PIPE_COMPUTE_CAP_SUBGROUP_SIZES: - RET((uint32_t[]){32}); // TODO - - case PIPE_COMPUTE_CAP_MAX_SUBGROUPS: - RET((uint32_t[]){0}); // TODO - - case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK: - RET((uint64_t[]){ compiler->max_variable_workgroup_size }); - } - - return 0; -} - static void fd_init_shader_caps(struct fd_screen *screen) { @@ -1237,8 +1017,6 @@ fd_screen_create(int fd, pscreen->destroy = fd_screen_destroy; pscreen->get_screen_fd = fd_screen_get_fd; pscreen->query_memory_info = fd_query_memory_info; - pscreen->get_shader_param = fd_screen_get_shader_param; - pscreen->get_compute_param = fd_get_compute_param; pscreen->get_compiler_options = fd_get_compiler_options; pscreen->get_disk_shader_cache = fd_get_disk_shader_cache;