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i965: Move intel_context::max_gtt_map_object_size to brw_context.

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Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>
This commit is contained in:
Kenneth Graunke 2013-07-03 14:44:07 -07:00
parent b15f1fc3c6
commit 0273e6e23e
4 changed files with 5 additions and 5 deletions
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2
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -865,6 +865,8 @@ struct brw_context
*/
bool perf_debug;
uint32_t max_gtt_map_object_size;
bool emit_state_always;
bool has_surface_tile_offset;
bool has_compr4;

2
src/mesa/drivers/dri/i965/intel_context.c
View file

@ -523,7 +523,7 @@ intelInitContext(struct brw_context *brw,
* taken up by things like the framebuffer and the ringbuffer and such, so
* be more conservative.
*/
intel->max_gtt_map_object_size = gtt_size / 4;
brw->max_gtt_map_object_size = gtt_size / 4;
brw->bufmgr = intelScreen->bufmgr;

2
src/mesa/drivers/dri/i965/intel_context.h
View file

@ -137,8 +137,6 @@ struct intel_context
char buffer[4096];
} upload;
uint32_t max_gtt_map_object_size;
int driFd;
__DRIcontext *driContext;

4
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
View file

@ -571,7 +571,7 @@ intel_miptree_create(struct brw_context *brw,
* BLT engine to support it. The BLT paths can't currently handle Y-tiling,
* so we need to fall back to X.
*/
if (y_or_x && mt->region->bo->size >= intel->max_gtt_map_object_size) {
if (y_or_x && mt->region->bo->size >= brw->max_gtt_map_object_size) {
perf_debug("%dx%d miptree larger than aperture; falling back to X-tiled\n",
mt->total_width, mt->total_height);
intel_region_release(&mt->region);
@ -2146,7 +2146,7 @@ intel_miptree_map_singlesample(struct brw_context *brw,
mt->region->pitch < 32768) {
intel_miptree_map_blit(brw, mt, map, level, slice);
} else if (mt->region->tiling != I915_TILING_NONE &&
mt->region->bo->size >= intel->max_gtt_map_object_size) {
mt->region->bo->size >= brw->max_gtt_map_object_size) {
assert(mt->region->pitch < 32768);
intel_miptree_map_blit(brw, mt, map, level, slice);
} else {