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i965/gen6/gs: Implement GS_OPCODE_SET_PRIMITIVE_ID.

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In gen6 the geometry shader payload includes the PrimitiveID information in
r0.1. When the shader code uses glPimitiveIdIn we will have to move this to
a separate hardware register where we can map this attribute. This opcode
takes the selected destination register and moves r0.1 there.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Iago Toral Quiroga 2014-07-24 12:14:27 +02:00
parent c091804f4c
commit 024b7c0f33
4 changed files with 27 additions and 0 deletions
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8
src/mesa/drivers/dri/i965/brw_defines.h
View file

@ -1035,6 +1035,14 @@ enum opcode {
* the header in the URB write operation we are allocating the handle for.
*/
GS_OPCODE_FF_SYNC,
/**
* Move r0.1 (which holds PrimitiveID information in gen6) to a separate
* register.
*
* - dst is the GRF where PrimitiveID information will be moved.
*/
GS_OPCODE_SET_PRIMITIVE_ID,
};
enum brw_derivative_quality {

2
src/mesa/drivers/dri/i965/brw_shader.cpp
View file

@ -526,6 +526,8 @@ brw_instruction_name(enum opcode op)
return "get_instance_id";
case GS_OPCODE_FF_SYNC:
return "ff_sync";
case GS_OPCODE_SET_PRIMITIVE_ID:
return "set_primitive_id";
default:
/* Yes, this leaks. It's in debug code, it should never occur, and if

1
src/mesa/drivers/dri/i965/brw_vec4.h
View file

@ -661,6 +661,7 @@ private:
void generate_gs_ff_sync(vec4_instruction *inst,
struct brw_reg dst,
struct brw_reg src0);
void generate_gs_set_primitive_id(struct brw_reg dst);
void generate_oword_dual_block_offsets(struct brw_reg m1,
struct brw_reg index);
void generate_scratch_write(vec4_instruction *inst,

16
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
View file

@ -721,6 +721,18 @@ vec4_generator::generate_gs_ff_sync(vec4_instruction *inst,
brw_pop_insn_state(p);
}
void
vec4_generator::generate_gs_set_primitive_id(struct brw_reg dst)
{
/* In gen6, PrimitiveID is delivered in R0.1 of the payload */
struct brw_reg src = brw_vec8_grf(0, 0);
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_access_mode(p, BRW_ALIGN_1);
brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
brw_pop_insn_state(p);
}
void
vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
struct brw_reg index)
@ -1351,6 +1363,10 @@ vec4_generator::generate_code(const cfg_t *cfg)
generate_gs_ff_sync(inst, dst, src[0]);
break;
case GS_OPCODE_SET_PRIMITIVE_ID:
generate_gs_set_primitive_id(dst);
break;
case GS_OPCODE_SET_DWORD_2:
generate_gs_set_dword_2(dst, src[0]);
break;