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intel/nir: Add a helper for getting BRW_AOP from an intrinsic
So many duplicated switch statements.... Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
parent
951cf94521
commit
021fa28163
4 changed files with 78 additions and 170 deletions
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@ -3654,20 +3654,6 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld,
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}
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}
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}
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}
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static int
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get_op_for_atomic_add(nir_intrinsic_instr *instr, unsigned src)
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{
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if (nir_src_is_const(instr->src[src])) {
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int64_t add_val = nir_src_as_int(instr->src[src]);
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if (add_val == 1)
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return BRW_AOP_INC;
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else if (add_val == -1)
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return BRW_AOP_DEC;
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}
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return BRW_AOP_ADD;
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}
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void
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void
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fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
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fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
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nir_intrinsic_instr *instr)
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nir_intrinsic_instr *instr)
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@ -3721,43 +3707,21 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
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}
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}
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case nir_intrinsic_shared_atomic_add:
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case nir_intrinsic_shared_atomic_add:
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nir_emit_shared_atomic(bld, get_op_for_atomic_add(instr, 1), instr);
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break;
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case nir_intrinsic_shared_atomic_imin:
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case nir_intrinsic_shared_atomic_imin:
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nir_emit_shared_atomic(bld, BRW_AOP_IMIN, instr);
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break;
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case nir_intrinsic_shared_atomic_umin:
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case nir_intrinsic_shared_atomic_umin:
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nir_emit_shared_atomic(bld, BRW_AOP_UMIN, instr);
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break;
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case nir_intrinsic_shared_atomic_imax:
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case nir_intrinsic_shared_atomic_imax:
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nir_emit_shared_atomic(bld, BRW_AOP_IMAX, instr);
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break;
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case nir_intrinsic_shared_atomic_umax:
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case nir_intrinsic_shared_atomic_umax:
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nir_emit_shared_atomic(bld, BRW_AOP_UMAX, instr);
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break;
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case nir_intrinsic_shared_atomic_and:
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case nir_intrinsic_shared_atomic_and:
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nir_emit_shared_atomic(bld, BRW_AOP_AND, instr);
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break;
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case nir_intrinsic_shared_atomic_or:
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case nir_intrinsic_shared_atomic_or:
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nir_emit_shared_atomic(bld, BRW_AOP_OR, instr);
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break;
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case nir_intrinsic_shared_atomic_xor:
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case nir_intrinsic_shared_atomic_xor:
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nir_emit_shared_atomic(bld, BRW_AOP_XOR, instr);
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break;
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case nir_intrinsic_shared_atomic_exchange:
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case nir_intrinsic_shared_atomic_exchange:
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nir_emit_shared_atomic(bld, BRW_AOP_MOV, instr);
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break;
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case nir_intrinsic_shared_atomic_comp_swap:
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case nir_intrinsic_shared_atomic_comp_swap:
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nir_emit_shared_atomic(bld, BRW_AOP_CMPWR, instr);
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nir_emit_shared_atomic(bld, brw_aop_for_nir_intrinsic(instr), instr);
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break;
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break;
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case nir_intrinsic_shared_atomic_fmin:
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case nir_intrinsic_shared_atomic_fmin:
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nir_emit_shared_atomic_float(bld, BRW_AOP_FMIN, instr);
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break;
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case nir_intrinsic_shared_atomic_fmax:
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case nir_intrinsic_shared_atomic_fmax:
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nir_emit_shared_atomic_float(bld, BRW_AOP_FMAX, instr);
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break;
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case nir_intrinsic_shared_atomic_fcomp_swap:
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case nir_intrinsic_shared_atomic_fcomp_swap:
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nir_emit_shared_atomic_float(bld, BRW_AOP_FCMPWR, instr);
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nir_emit_shared_atomic_float(bld, brw_aop_for_nir_intrinsic(instr), instr);
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break;
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break;
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case nir_intrinsic_load_shared: {
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case nir_intrinsic_load_shared: {
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@ -4046,61 +4010,11 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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bld.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
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bld.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
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fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
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fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
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} else {
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} else {
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int op;
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unsigned num_srcs = info->num_srcs;
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unsigned num_srcs = info->num_srcs;
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int op = brw_aop_for_nir_intrinsic(instr);
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switch (instr->intrinsic) {
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if (op == BRW_AOP_INC || op == BRW_AOP_DEC) {
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case nir_intrinsic_image_atomic_add:
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case nir_intrinsic_bindless_image_atomic_add:
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assert(num_srcs == 4);
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assert(num_srcs == 4);
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op = get_op_for_atomic_add(instr, 3);
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if (op != BRW_AOP_ADD)
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num_srcs = 3;
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num_srcs = 3;
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break;
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case nir_intrinsic_image_atomic_imin:
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case nir_intrinsic_bindless_image_atomic_imin:
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assert(format == GL_R32I);
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op = BRW_AOP_IMIN;
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break;
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case nir_intrinsic_image_atomic_umin:
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case nir_intrinsic_bindless_image_atomic_umin:
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assert(format == GL_R32UI);
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op = BRW_AOP_UMIN;
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break;
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case nir_intrinsic_image_atomic_imax:
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case nir_intrinsic_bindless_image_atomic_imax:
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assert(format == GL_R32I);
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op = BRW_AOP_IMAX;
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break;
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case nir_intrinsic_image_atomic_umax:
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case nir_intrinsic_bindless_image_atomic_umax:
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assert(format == GL_R32UI);
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op = BRW_AOP_UMAX;
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break;
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case nir_intrinsic_image_atomic_and:
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case nir_intrinsic_bindless_image_atomic_and:
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op = BRW_AOP_AND;
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break;
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case nir_intrinsic_image_atomic_or:
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case nir_intrinsic_bindless_image_atomic_or:
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op = BRW_AOP_OR;
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break;
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case nir_intrinsic_image_atomic_xor:
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case nir_intrinsic_bindless_image_atomic_xor:
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op = BRW_AOP_XOR;
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break;
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case nir_intrinsic_image_atomic_exchange:
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case nir_intrinsic_bindless_image_atomic_exchange:
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op = BRW_AOP_MOV;
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break;
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case nir_intrinsic_image_atomic_comp_swap:
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case nir_intrinsic_bindless_image_atomic_comp_swap:
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op = BRW_AOP_CMPWR;
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break;
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default:
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unreachable("Not reachable.");
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}
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}
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srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(op);
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srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(op);
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@ -4472,43 +4386,21 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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break;
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break;
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case nir_intrinsic_global_atomic_add:
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case nir_intrinsic_global_atomic_add:
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nir_emit_global_atomic(bld, get_op_for_atomic_add(instr, 1), instr);
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break;
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case nir_intrinsic_global_atomic_imin:
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case nir_intrinsic_global_atomic_imin:
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nir_emit_global_atomic(bld, BRW_AOP_IMIN, instr);
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break;
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case nir_intrinsic_global_atomic_umin:
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case nir_intrinsic_global_atomic_umin:
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nir_emit_global_atomic(bld, BRW_AOP_UMIN, instr);
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break;
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case nir_intrinsic_global_atomic_imax:
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case nir_intrinsic_global_atomic_imax:
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nir_emit_global_atomic(bld, BRW_AOP_IMAX, instr);
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break;
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case nir_intrinsic_global_atomic_umax:
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case nir_intrinsic_global_atomic_umax:
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nir_emit_global_atomic(bld, BRW_AOP_UMAX, instr);
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break;
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case nir_intrinsic_global_atomic_and:
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case nir_intrinsic_global_atomic_and:
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nir_emit_global_atomic(bld, BRW_AOP_AND, instr);
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break;
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case nir_intrinsic_global_atomic_or:
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case nir_intrinsic_global_atomic_or:
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nir_emit_global_atomic(bld, BRW_AOP_OR, instr);
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break;
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case nir_intrinsic_global_atomic_xor:
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case nir_intrinsic_global_atomic_xor:
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nir_emit_global_atomic(bld, BRW_AOP_XOR, instr);
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break;
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case nir_intrinsic_global_atomic_exchange:
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case nir_intrinsic_global_atomic_exchange:
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nir_emit_global_atomic(bld, BRW_AOP_MOV, instr);
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break;
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case nir_intrinsic_global_atomic_comp_swap:
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case nir_intrinsic_global_atomic_comp_swap:
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nir_emit_global_atomic(bld, BRW_AOP_CMPWR, instr);
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nir_emit_global_atomic(bld, brw_aop_for_nir_intrinsic(instr), instr);
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break;
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break;
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case nir_intrinsic_global_atomic_fmin:
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case nir_intrinsic_global_atomic_fmin:
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nir_emit_global_atomic_float(bld, BRW_AOP_FMIN, instr);
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break;
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case nir_intrinsic_global_atomic_fmax:
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case nir_intrinsic_global_atomic_fmax:
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nir_emit_global_atomic_float(bld, BRW_AOP_FMAX, instr);
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break;
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case nir_intrinsic_global_atomic_fcomp_swap:
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case nir_intrinsic_global_atomic_fcomp_swap:
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nir_emit_global_atomic_float(bld, BRW_AOP_FCMPWR, instr);
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nir_emit_global_atomic_float(bld, brw_aop_for_nir_intrinsic(instr), instr);
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break;
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break;
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case nir_intrinsic_load_ssbo: {
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case nir_intrinsic_load_ssbo: {
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@ -4602,43 +4494,21 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr
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}
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}
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case nir_intrinsic_ssbo_atomic_add:
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case nir_intrinsic_ssbo_atomic_add:
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nir_emit_ssbo_atomic(bld, get_op_for_atomic_add(instr, 2), instr);
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break;
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case nir_intrinsic_ssbo_atomic_imin:
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case nir_intrinsic_ssbo_atomic_imin:
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nir_emit_ssbo_atomic(bld, BRW_AOP_IMIN, instr);
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break;
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case nir_intrinsic_ssbo_atomic_umin:
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case nir_intrinsic_ssbo_atomic_umin:
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nir_emit_ssbo_atomic(bld, BRW_AOP_UMIN, instr);
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break;
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case nir_intrinsic_ssbo_atomic_imax:
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case nir_intrinsic_ssbo_atomic_imax:
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nir_emit_ssbo_atomic(bld, BRW_AOP_IMAX, instr);
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break;
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case nir_intrinsic_ssbo_atomic_umax:
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case nir_intrinsic_ssbo_atomic_umax:
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nir_emit_ssbo_atomic(bld, BRW_AOP_UMAX, instr);
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break;
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case nir_intrinsic_ssbo_atomic_and:
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case nir_intrinsic_ssbo_atomic_and:
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nir_emit_ssbo_atomic(bld, BRW_AOP_AND, instr);
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break;
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case nir_intrinsic_ssbo_atomic_or:
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case nir_intrinsic_ssbo_atomic_or:
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nir_emit_ssbo_atomic(bld, BRW_AOP_OR, instr);
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break;
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case nir_intrinsic_ssbo_atomic_xor:
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case nir_intrinsic_ssbo_atomic_xor:
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nir_emit_ssbo_atomic(bld, BRW_AOP_XOR, instr);
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break;
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case nir_intrinsic_ssbo_atomic_exchange:
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case nir_intrinsic_ssbo_atomic_exchange:
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nir_emit_ssbo_atomic(bld, BRW_AOP_MOV, instr);
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break;
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case nir_intrinsic_ssbo_atomic_comp_swap:
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case nir_intrinsic_ssbo_atomic_comp_swap:
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nir_emit_ssbo_atomic(bld, BRW_AOP_CMPWR, instr);
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nir_emit_ssbo_atomic(bld, brw_aop_for_nir_intrinsic(instr), instr);
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break;
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break;
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case nir_intrinsic_ssbo_atomic_fmin:
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case nir_intrinsic_ssbo_atomic_fmin:
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nir_emit_ssbo_atomic_float(bld, BRW_AOP_FMIN, instr);
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break;
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case nir_intrinsic_ssbo_atomic_fmax:
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case nir_intrinsic_ssbo_atomic_fmax:
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nir_emit_ssbo_atomic_float(bld, BRW_AOP_FMAX, instr);
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break;
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case nir_intrinsic_ssbo_atomic_fcomp_swap:
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case nir_intrinsic_ssbo_atomic_fcomp_swap:
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nir_emit_ssbo_atomic_float(bld, BRW_AOP_FCMPWR, instr);
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nir_emit_ssbo_atomic_float(bld, brw_aop_for_nir_intrinsic(instr), instr);
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break;
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break;
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case nir_intrinsic_get_buffer_size: {
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case nir_intrinsic_get_buffer_size: {
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@ -1090,6 +1090,72 @@ brw_cmod_for_nir_comparison(nir_op op)
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}
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}
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}
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}
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uint32_t
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brw_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic)
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{
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switch (atomic->intrinsic) {
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#define AOP_CASE(atom) \
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case nir_intrinsic_image_atomic_##atom: \
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case nir_intrinsic_bindless_image_atomic_##atom: \
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case nir_intrinsic_ssbo_atomic_##atom: \
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case nir_intrinsic_shared_atomic_##atom: \
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case nir_intrinsic_global_atomic_##atom
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AOP_CASE(add): {
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unsigned src_idx;
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switch (atomic->intrinsic) {
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case nir_intrinsic_image_atomic_add:
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case nir_intrinsic_bindless_image_atomic_add:
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src_idx = 3;
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break;
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case nir_intrinsic_ssbo_atomic_add:
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src_idx = 2;
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break;
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case nir_intrinsic_shared_atomic_add:
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case nir_intrinsic_global_atomic_add:
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src_idx = 1;
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break;
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default:
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unreachable("Invalid add atomic opcode");
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}
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if (nir_src_is_const(atomic->src[src_idx])) {
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int64_t add_val = nir_src_as_int(atomic->src[src_idx]);
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if (add_val == 1)
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return BRW_AOP_INC;
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else if (add_val == -1)
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return BRW_AOP_DEC;
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}
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return BRW_AOP_ADD;
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}
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AOP_CASE(imin): return BRW_AOP_IMIN;
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AOP_CASE(umin): return BRW_AOP_UMIN;
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AOP_CASE(imax): return BRW_AOP_IMAX;
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AOP_CASE(umax): return BRW_AOP_UMAX;
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AOP_CASE(and): return BRW_AOP_AND;
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AOP_CASE(or): return BRW_AOP_OR;
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AOP_CASE(xor): return BRW_AOP_XOR;
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AOP_CASE(exchange): return BRW_AOP_MOV;
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AOP_CASE(comp_swap): return BRW_AOP_CMPWR;
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#undef AOP_CASE
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#define AOP_CASE(atom) \
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case nir_intrinsic_ssbo_atomic_##atom: \
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case nir_intrinsic_shared_atomic_##atom: \
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case nir_intrinsic_global_atomic_##atom
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AOP_CASE(fmin): return BRW_AOP_FMIN;
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AOP_CASE(fmax): return BRW_AOP_FMAX;
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AOP_CASE(fcomp_swap): return BRW_AOP_FCMPWR;
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#undef AOP_CASE
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default:
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unreachable("Unsupported NIR atomic intrinsic");
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}
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}
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enum brw_reg_type
|
enum brw_reg_type
|
||||||
brw_type_for_nir_type(const struct gen_device_info *devinfo, nir_alu_type type)
|
brw_type_for_nir_type(const struct gen_device_info *devinfo, nir_alu_type type)
|
||||||
{
|
{
|
||||||
|
|
|
||||||
|
|
@ -147,6 +147,7 @@ void brw_nir_apply_key(nir_shader *nir,
|
||||||
bool is_scalar);
|
bool is_scalar);
|
||||||
|
|
||||||
enum brw_conditional_mod brw_cmod_for_nir_comparison(nir_op op);
|
enum brw_conditional_mod brw_cmod_for_nir_comparison(nir_op op);
|
||||||
|
uint32_t brw_aop_for_nir_intrinsic(const nir_intrinsic_instr *atomic);
|
||||||
enum brw_reg_type brw_type_for_nir_type(const struct gen_device_info *devinfo,
|
enum brw_reg_type brw_type_for_nir_type(const struct gen_device_info *devinfo,
|
||||||
nir_alu_type type);
|
nir_alu_type type);
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -548,46 +548,17 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
case nir_intrinsic_ssbo_atomic_add: {
|
case nir_intrinsic_ssbo_atomic_add:
|
||||||
int op = BRW_AOP_ADD;
|
|
||||||
|
|
||||||
if (nir_src_is_const(instr->src[2])) {
|
|
||||||
int add_val = nir_src_as_int(instr->src[2]);
|
|
||||||
if (add_val == 1)
|
|
||||||
op = BRW_AOP_INC;
|
|
||||||
else if (add_val == -1)
|
|
||||||
op = BRW_AOP_DEC;
|
|
||||||
}
|
|
||||||
|
|
||||||
nir_emit_ssbo_atomic(op, instr);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case nir_intrinsic_ssbo_atomic_imin:
|
case nir_intrinsic_ssbo_atomic_imin:
|
||||||
nir_emit_ssbo_atomic(BRW_AOP_IMIN, instr);
|
|
||||||
break;
|
|
||||||
case nir_intrinsic_ssbo_atomic_umin:
|
case nir_intrinsic_ssbo_atomic_umin:
|
||||||
nir_emit_ssbo_atomic(BRW_AOP_UMIN, instr);
|
|
||||||
break;
|
|
||||||
case nir_intrinsic_ssbo_atomic_imax:
|
case nir_intrinsic_ssbo_atomic_imax:
|
||||||
nir_emit_ssbo_atomic(BRW_AOP_IMAX, instr);
|
|
||||||
break;
|
|
||||||
case nir_intrinsic_ssbo_atomic_umax:
|
case nir_intrinsic_ssbo_atomic_umax:
|
||||||
nir_emit_ssbo_atomic(BRW_AOP_UMAX, instr);
|
|
||||||
break;
|
|
||||||
case nir_intrinsic_ssbo_atomic_and:
|
case nir_intrinsic_ssbo_atomic_and:
|
||||||
nir_emit_ssbo_atomic(BRW_AOP_AND, instr);
|
|
||||||
break;
|
|
||||||
case nir_intrinsic_ssbo_atomic_or:
|
case nir_intrinsic_ssbo_atomic_or:
|
||||||
nir_emit_ssbo_atomic(BRW_AOP_OR, instr);
|
|
||||||
break;
|
|
||||||
case nir_intrinsic_ssbo_atomic_xor:
|
case nir_intrinsic_ssbo_atomic_xor:
|
||||||
nir_emit_ssbo_atomic(BRW_AOP_XOR, instr);
|
|
||||||
break;
|
|
||||||
case nir_intrinsic_ssbo_atomic_exchange:
|
case nir_intrinsic_ssbo_atomic_exchange:
|
||||||
nir_emit_ssbo_atomic(BRW_AOP_MOV, instr);
|
|
||||||
break;
|
|
||||||
case nir_intrinsic_ssbo_atomic_comp_swap:
|
case nir_intrinsic_ssbo_atomic_comp_swap:
|
||||||
nir_emit_ssbo_atomic(BRW_AOP_CMPWR, instr);
|
nir_emit_ssbo_atomic(brw_aop_for_nir_intrinsic(instr), instr);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case nir_intrinsic_load_vertex_id:
|
case nir_intrinsic_load_vertex_id:
|
||||||
|
|
|
||||||
Loading…
Add table
Reference in a new issue