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freedreno/ir3/tests: Switch disasm test over to new decoder
Also, uncomment the `stc` test vectors (since the new decoder decodes these properly) and comment out an instruction which looks suspiciously like -6.0 in hex. This also switches the parser back to `atomic.b.op` from `atomic.op.b` which was a short-term workaround to make it easier for the legacy disassembler. Also switch the binary encoding for ldib to clear b0, because the new disassembler warns about unexpected dontcare bits (which cases the disasm to not match). Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7997>
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parent
704e49bae0
commit
01e8bd55de
3 changed files with 25 additions and 25 deletions
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@ -316,17 +316,17 @@ static int parse_w(const char *str)
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"resinfo.b" return TOKEN(T_OP_RESINFO_B);
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"resinfo.b" return TOKEN(T_OP_RESINFO_B);
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"ldib.b" return TOKEN(T_OP_LDIB_B);
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"ldib.b" return TOKEN(T_OP_LDIB_B);
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"stib.b" return TOKEN(T_OP_STIB_B);
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"stib.b" return TOKEN(T_OP_STIB_B);
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"atomic.add.b" return TOKEN(T_OP_ATOMIC_B_ADD);
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"atomic.b.add" return TOKEN(T_OP_ATOMIC_B_ADD);
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"atomic.sub.b" return TOKEN(T_OP_ATOMIC_B_SUB);
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"atomic.b.sub" return TOKEN(T_OP_ATOMIC_B_SUB);
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"atomic.xchg.b" return TOKEN(T_OP_ATOMIC_B_XCHG);
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"atomic.b.xchg" return TOKEN(T_OP_ATOMIC_B_XCHG);
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"atomic.inc.b" return TOKEN(T_OP_ATOMIC_B_INC);
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"atomic.b.inc" return TOKEN(T_OP_ATOMIC_B_INC);
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"atomic.dec.b" return TOKEN(T_OP_ATOMIC_B_DEC);
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"atomic.b.dec" return TOKEN(T_OP_ATOMIC_B_DEC);
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"atomic.cmpxchg.b" return TOKEN(T_OP_ATOMIC_B_CMPXCHG);
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"atomic.b.cmpxchg" return TOKEN(T_OP_ATOMIC_B_CMPXCHG);
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"atomic.min.b" return TOKEN(T_OP_ATOMIC_B_MIN);
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"atomic.b.min" return TOKEN(T_OP_ATOMIC_B_MIN);
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"atomic.max.b" return TOKEN(T_OP_ATOMIC_B_MAX);
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"atomic.b.max" return TOKEN(T_OP_ATOMIC_B_MAX);
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"atomic.and.b" return TOKEN(T_OP_ATOMIC_B_AND);
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"atomic.b.and" return TOKEN(T_OP_ATOMIC_B_AND);
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"atomic.or.b" return TOKEN(T_OP_ATOMIC_B_OR);
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"atomic.b.or" return TOKEN(T_OP_ATOMIC_B_OR);
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"atomic.xor.b" return TOKEN(T_OP_ATOMIC_B_XOR);
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"atomic.b.xor" return TOKEN(T_OP_ATOMIC_B_XOR);
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"ldgb" return TOKEN(T_OP_LDGB);
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"ldgb" return TOKEN(T_OP_LDGB);
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"stgb" return TOKEN(T_OP_STGB);
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"stgb" return TOKEN(T_OP_STGB);
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"stib" return TOKEN(T_OP_STIB);
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"stib" return TOKEN(T_OP_STIB);
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@ -120,7 +120,7 @@ test('ir3_disasm',
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executable(
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executable(
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'ir3_disasm',
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'ir3_disasm',
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'tests/disasm.c',
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'tests/disasm.c',
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link_with: libfreedreno_ir3,
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link_with: [libfreedreno_ir3, libir3decode],
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dependencies: [idep_mesautil, idep_nir],
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dependencies: [idep_mesautil, idep_nir],
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include_directories: [inc_freedreno, inc_include, inc_src, inc_gallium],
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include_directories: [inc_freedreno, inc_include, inc_src, inc_gallium],
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),
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),
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@ -35,12 +35,13 @@
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#include <stdlib.h>
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#include <stdlib.h>
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#include <string.h>
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#include <string.h>
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#include "util/macros.h"
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#include "util/macros.h"
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#include "disasm.h"
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#include "ir3.h"
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#include "ir3.h"
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#include "ir3_assembler.h"
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#include "ir3_assembler.h"
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#include "ir3_shader.h"
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#include "ir3_shader.h"
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#include "isa/isa.h"
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#define INSTR_5XX(i, d, ...) { .gpu_id = 540, .instr = #i, .expected = d, __VA_ARGS__ }
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#define INSTR_5XX(i, d, ...) { .gpu_id = 540, .instr = #i, .expected = d, __VA_ARGS__ }
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#define INSTR_6XX(i, d, ...) { .gpu_id = 630, .instr = #i, .expected = d, __VA_ARGS__ }
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#define INSTR_6XX(i, d, ...) { .gpu_id = 630, .instr = #i, .expected = d, __VA_ARGS__ }
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@ -140,7 +141,8 @@ static const struct test {
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INSTR_5XX(c6e60000_00010600, "ldgb.untyped.4d.u32.1 r0.x, g[0], r1.x, r0.x"),
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INSTR_5XX(c6e60000_00010600, "ldgb.untyped.4d.u32.1 r0.x, g[0], r1.x, r0.x"),
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INSTR_5XX(d7660204_02000a01, "(sy)stib.typed.2d.u32.1 g[1], r0.x, r0.z, r1.x"),
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INSTR_5XX(d7660204_02000a01, "(sy)stib.typed.2d.u32.1 g[1], r0.x, r0.z, r1.x"),
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INSTR_6XX(c0c00000_00000000, "stg.f16 g[hr0.x], hr0.x, hr0.x", .parse_fail=true),
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// TODO is this a real instruction? Or float -6.0 ?
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// INSTR_6XX(c0c00000_00000000, "stg.f16 g[hr0.x], hr0.x, hr0.x", .parse_fail=true),
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/* dEQP-GLES31.functional.tessellation.invariance.outer_edge_symmetry.isolines_equal_spacing_ccw */
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/* dEQP-GLES31.functional.tessellation.invariance.outer_edge_symmetry.isolines_equal_spacing_ccw */
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INSTR_6XX(c0d20906_02800004, "stg.f32 g[r1.x+r1.z], r0.z, 2"), /* stg.a.f32 g[r1.x+(r1.z<<2)], r0.z, 2 */
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INSTR_6XX(c0d20906_02800004, "stg.f32 g[r1.x+r1.z], r0.z, 2"), /* stg.a.f32 g[r1.x+(r1.z<<2)], r0.z, 2 */
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INSTR_6XX(c0da052e_01800042, "stg.s32 g[r0.z+r11.z], r8.y, 1"), /* stg.a.s32 g[r0.z+(r11.z<<2)], r8.y, 1 */
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INSTR_6XX(c0da052e_01800042, "stg.s32 g[r0.z+r11.z], r8.y, 1"), /* stg.a.s32 g[r0.z+(r11.z<<2)], r8.y, 1 */
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@ -159,15 +161,10 @@ static const struct test {
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INSTR_6XX(c0060006_0181800f, "ldg.u32 r1.z, g[r1.z+7], 1"),
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INSTR_6XX(c0060006_0181800f, "ldg.u32 r1.z, g[r1.z+7], 1"),
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INSTR_6XX(c0060006_01818001, "ldg.u32 r1.z, g[r1.z], 1"),
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INSTR_6XX(c0060006_01818001, "ldg.u32 r1.z, g[r1.z], 1"),
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/* TODO: We don't support disasm of stc yet and produce a stgb instead
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* (same as their disasm does for other families. They're used as part
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* uniforms setup, followed by a shpe and then a load of the constant that
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* was stored in the dynamic part of the shader.
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*/
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/* dEQP-GLES3.functional.ubo.random.basic_arrays.0 */
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/* dEQP-GLES3.functional.ubo.random.basic_arrays.0 */
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/* INSTR_6XX(c7020020_01800000, "stc c[32], r0.x, 1"), */
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INSTR_6XX(c7020020_01800000, "stc c[32], r0.x, 1", .parse_fail=true),
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/* dEQP-VK.image.image_size.cube_array.readonly_writeonly_1x1x12 */
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/* dEQP-VK.image.image_size.cube_array.readonly_writeonly_1x1x12 */
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/* INSTR_6XX(c7060020_03800000, "stc c[32], r0.x, 3"), */
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INSTR_6XX(c7060020_03800000, "stc c[32], r0.x, 3", .parse_fail=true),
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/* dEQP-VK.image.image_size.cube_array.readonly_writeonly_1x1x12 */
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/* dEQP-VK.image.image_size.cube_array.readonly_writeonly_1x1x12 */
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INSTR_6XX(c0260200_03676100, "stib.b.untyped.1d.u32.3.imm.base0 r0.x, r0.w, 1"), /* stib.untyped.u32.1d.3.mode4.base0 r0.x, r0.w, 1 */
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INSTR_6XX(c0260200_03676100, "stib.b.untyped.1d.u32.3.imm.base0 r0.x, r0.w, 1"), /* stib.untyped.u32.1d.3.mode4.base0 r0.x, r0.w, 1 */
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@ -297,9 +294,9 @@ static const struct test {
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INSTR_6XX(d5c60003_03008001, "(sy)atomic.max.untyped.1d.u32.1.l r0.w, l[r0.z], r0.w"),
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INSTR_6XX(d5c60003_03008001, "(sy)atomic.max.untyped.1d.u32.1.l r0.w, l[r0.z], r0.w"),
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/* Bindless atomic: */
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/* Bindless atomic: */
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INSTR_6XX(c03a0003_01640001, "atomic.add.b.untyped.1d.s32.1.imm r0.w, r0.y, 0"), /* atomic.b.add.g.s32.1d.mode0.base0 r0.w,r0.y,0 */
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INSTR_6XX(c03a0003_01640001, "atomic.b.add.untyped.1d.s32.1.imm r0.w, r0.y, 0"), /* atomic.b.add.g.s32.1d.mode0.base0 r0.w,r0.y,0 */
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INSTR_6XX(c03a0003_01660001, "atomic.and.b.untyped.1d.s32.1.imm r0.w, r0.y, 0"), /* atomic.b.and.g.s32.1d.mode0.base0 r0.w,r0.y,0 */
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INSTR_6XX(c03a0003_01660001, "atomic.b.and.untyped.1d.s32.1.imm r0.w, r0.y, 0"), /* atomic.b.and.g.s32.1d.mode0.base0 r0.w,r0.y,0 */
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INSTR_6XX(c0360000_0365c801, "atomic.max.b.typed.1d.u32.1.imm r0.x, r0.w, 0"), /* atomic.b.max.g.u32.1d.mode0.base0 r0.x,r0.w,0 */
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INSTR_6XX(c0360000_0365c801, "atomic.b.max.typed.1d.u32.1.imm r0.x, r0.w, 0"), /* atomic.b.max.g.u32.1d.mode0.base0 r0.x,r0.w,0 */
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/* dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_literal.fragment.sampler2d */
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/* dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_literal.fragment.sampler2d */
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INSTR_6XX(a0c01f04_0cc00005, "sam (f32)(xyzw)r1.x, r0.z, s#6, t#6"),
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INSTR_6XX(a0c01f04_0cc00005, "sam (f32)(xyzw)r1.x, r0.z, s#6, t#6"),
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@ -351,7 +348,10 @@ main(int argc, char **argv)
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strtoll(&test->instr[9], NULL, 16),
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strtoll(&test->instr[9], NULL, 16),
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strtoll(&test->instr[0], NULL, 16),
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strtoll(&test->instr[0], NULL, 16),
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};
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};
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disasm_a3xx(code, ARRAY_SIZE(code), 0, fdisasm, test->gpu_id);
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isa_decode(code, 8, fdisasm, &(struct isa_decode_options){
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.gpu_id = test->gpu_id,
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.show_errors = true,
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});
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fflush(fdisasm);
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fflush(fdisasm);
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trim(disasm_output);
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trim(disasm_output);
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