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nouveau/mme: Add isaspec XML for the Turing+ MME
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24326>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
af961f9aec
commit
01d0c78386
1 changed files with 180 additions and 0 deletions
180
src/nouveau/mme/mme_tu104.xml
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src/nouveau/mme/mme_tu104.xml
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<?xml version="1.0" encoding="UTF-8"?>
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<!--
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Copyright © 2022 Collabor, Ltd.
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice (including the next
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paragraph) shall be included in all copies or substantial portions of the
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Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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-->
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<isa>
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<enum name="#pred">
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<value val="0" display="UUUU"/>
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<value val="1" display="TTTT"/>
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<value val="2" display="FFFF"/>
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<value val="3" display="TTUU"/>
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<value val="4" display="FFUU"/>
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<value val="5" display="TFUU"/>
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<value val="6" display="TUUU"/>
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<value val="7" display="FUUU"/>
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<value val="8" display="UUTT"/>
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<value val="9" display="UUTF"/>
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<value val="10" display="UUTU"/>
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<value val="11" display="UUFT"/>
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<value val="12" display="UUFF"/>
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<value val="13" display="UUFU"/>
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<value val="14" display="UUUT"/>
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<value val="15" display="UUUF"/>
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</enum>
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<enum name="#reg">
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<value val="0" display="r0"/>
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<value val="1" display="r1"/>
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<value val="2" display="r2"/>
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<value val="3" display="r3"/>
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<value val="4" display="r4"/>
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<value val="5" display="r5"/>
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<value val="6" display="r6"/>
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<value val="7" display="r7"/>
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<value val="8" display="r8"/>
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<value val="9" display="r9"/>
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<value val="10" display="r10"/>
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<value val="11" display="r11"/>
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<value val="12" display="r12"/>
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<value val="13" display="r13"/>
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<value val="14" display="r14"/>
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<value val="15" display="r15"/>
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<value val="16" display="r16"/>
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<value val="17" display="r17"/>
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<value val="18" display="r18"/>
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<value val="19" display="r19"/>
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<value val="20" display="r20"/>
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<value val="21" display="r21"/>
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<value val="22" display="r22"/>
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<value val="23" display="r23"/>
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<value val="24" display="zero"/>
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<value val="25" display="imm"/>
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<value val="26" display="immpair"/>
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<value val="27" display="imm32"/>
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<value val="28" display="load0"/>
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<value val="29" display="load1"/>
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</enum>
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<enum name="#alu-op">
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<value val="0" display="ADD"/>
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<value val="1" display="ADDC"/>
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<value val="2" display="SUB"/>
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<value val="3" display="SUBB"/>
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<value val="4" display="MUL"/>
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<value val="5" display="MULH"/>
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<value val="6" display="MULU"/>
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<value val="7" display="EXTENDED"/>
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<value val="8" display="CLZ"/>
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<value val="9" display="SLL"/>
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<value val="10" display="SRL"/>
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<value val="11" display="SRA"/>
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<value val="12" display="AND"/>
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<value val="13" display="NAND"/>
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<value val="14" display="OR"/>
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<value val="15" display="XOR"/>
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<value val="16" display="MERGE"/>
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<value val="17" display="SLT"/>
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<value val="18" display="SLTU"/>
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<value val="19" display="SLE"/>
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<value val="20" display="SLEU"/>
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<value val="21" display="SEQ"/>
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<value val="22" display="STATE"/>
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<value val="23" display="LOOP"/>
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<value val="24" display="JAL"/>
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<value val="25" display="BLT"/>
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<value val="26" display="BLTU"/>
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<value val="27" display="BLE"/>
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<value val="28" display="BLEU"/>
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<value val="29" display="BEQ"/>
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<value val="30" display="DREAD"/>
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<value val="31" display="DWRITE"/>
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</enum>
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<enum name="#out-op">
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<value val="0" display="none"/>
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<value val="1" display="alu0"/>
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<value val="2" display="alu1"/>
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<value val="3" display="load0"/>
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<value val="4" display="load1"/>
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<value val="5" display="imm0"/>
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<value val="6" display="imm1"/>
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<!-- val="7" display="reserved" -->
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<value val="8" display="immhigh0"/>
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<value val="9" display="immhigh1"/>
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<value val="10" display="imm32"/>
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</enum>
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<bitset name="#alu" size="20">
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<display>
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{DST} = {OP} {SRC0} {SRC1}
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</display>
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<field name="OP" low="0" high="4" type="#alu-op"/>
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<field name="DST" low="5" high="9" type="#reg"/>
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<field name="SRC0" low="10" high="14" type="#reg"/>
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<field name="SRC1" low="15" high="19" type="#reg"/>
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<encode type="struct mme_tu104_alu">
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<map name="DST">src.dst</map>
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<map name="OP">src.op</map>
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<map name="SRC0">src.src[0]</map>
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<map name="SRC1">src.src[1]</map>
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</encode>
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</bitset>
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<bitset name="#out" size="7">
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<display>
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{EMIT} -> {MTHD}
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</display>
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<field name="MTHD" low="0" high="2" type="#out-op"/>
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<field name="EMIT" low="3" high="6" type="#out-op"/>
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<encode type="struct mme_tu104_out">
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<map name="MTHD">src.mthd</map>
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<map name="EMIT">src.emit</map>
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</encode>
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</bitset>
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<bitset name="#instruction" size="96">
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<display>
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{END_NEXT}({PRED} {PRED_MODE}) imm=[{IMM0}, {IMM1}], {ALU0}, {ALU1}, {OUT0}, {OUT1}
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</display>
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<field name="END_NEXT" pos="0" type="bool" display="(end-next)"/>
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<field name="PRED_MODE" low="1" high="4" type="#pred"/>
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<field name="PRED" low="5" high="9" type="#reg"/>
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<field name="ALU0" low="10" high="29" type="#alu"/>
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<field name="IMM0" low="30" high="45" type="uint"/>
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<field name="ALU1" low="46" high="65" type="#alu"/>
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<field name="IMM1" low="66" high="81" type="uint"/>
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<field name="OUT0" low="82" high="88" type="#out"/>
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<field name="OUT1" low="89" high="95" type="#out"/>
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<encode type="struct mme_tu104_inst">
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<map name="END_NEXT">src.end_next</map>
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<map name="PRED_MODE">src.pred_mode</map>
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<map name="PRED">src.pred</map>
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<map name="ALU0">src.alu[0]</map>
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<map name="IMM0">src.imm[0]</map>
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<map name="ALU1">src.alu[1]</map>
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<map name="IMM1">src.imm[1]</map>
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<map name="OUT0">src.out[0]</map>
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<map name="OUT1">src.out[1]</map>
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</encode>
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</bitset>
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</isa>
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