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ac, radeonsi: prepare cs_preamble_state for userq reg shadowing

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register shadowing has to be enabled in CONTEXT_CONTROL packet
in cs_preamble_state for user queue.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35106>
This commit is contained in:
Yogesh Mohan Marimuthu 2025-06-16 14:43:13 +05:30 • committed by Marge Bot
parent aab890644b
commit 0186977988
4 changed files with 32 additions and 5 deletions
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4
docs/envvars.rst
View file

@ -1744,6 +1744,10 @@ RadeonSI driver environment variables
Enable DPBB. Enable DPBB for gfx9 dGPU. Default enabled for gfx9 APU and >= gfx10.
``extra_md``
add extra information in bo metadata to help tools (umr)
``shadowregs``
Enable CP register shadowing in kernel queue.
``userqnoshadowregs``
Disable register shadowing in userqueue. This will also disable userqueue mcbp.
r600 driver environment variables
---------------------------------

9
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -54,6 +54,7 @@ static const struct debug_named_value radeonsi_debug_options[] = {
{"check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info."},
{"reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context."},
{"shadowregs", DBG(SHADOW_REGS), "Enable CP register shadowing."},
{"userqnoshadowregs", DBG(USERQ_NO_SHADOW_REGS), "Disable register shadowing in userqueue."},
{"nofastdlist", DBG(NO_FAST_DISPLAY_LIST), "Disable fast display lists"},
{"nodmashaders", DBG(NO_DMA_SHADERS), "Disable uploading shaders via CP DMA and map them directly."},
@ -523,8 +524,12 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, unsign
!sscreen->info.ip[AMD_IP_COMPUTE].num_queues ||
!(flags & PIPE_CONTEXT_COMPUTE_ONLY);
if (sctx->is_gfx_queue)
sctx->uses_kernelq_reg_shadowing = sscreen->info.has_kernelq_reg_shadowing;
if (sctx->is_gfx_queue) {
if (sscreen->info.userq_ip_mask & (1 << AMD_IP_GFX))
sctx->uses_userq_reg_shadowing = !(sscreen->debug_flags & DBG(USERQ_NO_SHADOW_REGS));
else
sctx->uses_kernelq_reg_shadowing = sscreen->info.has_kernelq_reg_shadowing;
}
if (flags & PIPE_CONTEXT_DEBUG)
sscreen->record_llvm_ir = true; /* racy but not critical */

2
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -182,6 +182,7 @@ enum
DBG_CHECK_VM,
DBG_RESERVE_VMID,
DBG_SHADOW_REGS,
DBG_USERQ_NO_SHADOW_REGS,
DBG_NO_FAST_DISPLAY_LIST,
DBG_NO_DMA_SHADERS,
@ -1002,6 +1003,7 @@ struct si_context {
bool is_noop:1;
bool is_gfx_queue:1;
bool uses_kernelq_reg_shadowing:1;
bool uses_userq_reg_shadowing:1;
bool gfx_flush_in_progress : 1;
bool gfx_last_ib_is_busy : 1;
bool compute_is_busy : 1;

22
src/gallium/drivers/radeonsi/si_state.c
View file

@ -5105,7 +5105,15 @@ static bool gfx10_init_gfx_preamble_state(struct si_context *sctx)
return false;
}
if (sctx->is_gfx_queue && !sctx->uses_kernelq_reg_shadowing) {
if (sctx->uses_userq_reg_shadowing) {
ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1) | CC0_LOAD_PER_CONTEXT_STATE(1) |
CC0_LOAD_CS_SH_REGS(1) | CC0_LOAD_GFX_SH_REGS(1) |
CC0_LOAD_GLOBAL_UCONFIG(1));
ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1) | CC1_SHADOW_PER_CONTEXT_STATE(1) |
CC1_SHADOW_CS_SH_REGS(1) | CC1_SHADOW_GFX_SH_REGS(1) |
CC1_SHADOW_GLOBAL_UCONFIG(1) | CC1_SHADOW_GLOBAL_CONFIG(1));
} else if (sctx->is_gfx_queue && !sctx->uses_kernelq_reg_shadowing) {
ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1));
ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1));
@ -5177,13 +5185,21 @@ static bool gfx12_init_gfx_preamble_state(struct si_context *sctx)
return false;
}
if (sctx->is_gfx_queue && !sctx->uses_kernelq_reg_shadowing) {
if (sctx->uses_userq_reg_shadowing) {
ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1) | CC0_LOAD_PER_CONTEXT_STATE(1) |
CC0_LOAD_CS_SH_REGS(1) | CC0_LOAD_GFX_SH_REGS(1) |
CC0_LOAD_GLOBAL_UCONFIG(1));
ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1) | CC1_SHADOW_PER_CONTEXT_STATE(1) |
CC1_SHADOW_CS_SH_REGS(1) | CC1_SHADOW_GFX_SH_REGS(1) |
CC1_SHADOW_GLOBAL_UCONFIG(1) | CC1_SHADOW_GLOBAL_CONFIG(1));
} else if (sctx->is_gfx_queue && !sctx->uses_kernelq_reg_shadowing) {
ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1));
ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1));
}
if (sctx->is_gfx_queue && sscreen->dpbb_allowed) {
if (sctx->is_gfx_queue && sscreen->dpbb_allowed && !sctx->uses_userq_reg_shadowing) {
ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_EVENT_WRITE, 0, 0));
ac_pm4_cmd_add(&pm4->base, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
}