fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-09 06:48:06 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radeonsi: Move display dcc dirty tracking to framebuffer emission.

Browse source 
To improve performance.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6783>
This commit is contained in:
Bas Nieuwenhuizen 2020-08-07 03:05:37 +02:00 • committed by Marek Olšák
parent c6c1fa9a26
commit 017ca86b22
3 changed files with 23 additions and 19 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -706,7 +706,6 @@ struct si_framebuffer {
ubyte nr_color_samples; /* at most 8xAA */ ubyte nr_color_samples; /* at most 8xAA */
ubyte compressed_cb_mask; ubyte compressed_cb_mask;
ubyte uncompressed_cb_mask; ubyte uncompressed_cb_mask;
ubyte displayable_dcc_cb_mask;
ubyte color_is_int8; ubyte color_is_int8;
ubyte color_is_int10; ubyte color_is_int10;
ubyte dirty_cbufs; ubyte dirty_cbufs;

27
src/gallium/drivers/radeonsi/si_state.c
View file

@ -2567,6 +2567,27 @@ static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *sta
} }
} }
static void si_update_display_dcc_dirty(struct si_context *sctx)
{
const struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
struct si_surface *surf;
struct si_texture *tex;
int i;
for (i = 0; i < state->nr_cbufs; i++) {
if (!state->cbufs[i])
continue;
surf = (struct si_surface *)state->cbufs[i];
tex = (struct si_texture *)surf->base.texture;
if (!tex->surface.display_dcc_offset)
continue;
tex->displayable_dcc_dirty = true;
}
}
static void si_set_framebuffer_state(struct pipe_context *ctx, static void si_set_framebuffer_state(struct pipe_context *ctx,
const struct pipe_framebuffer_state *state) const struct pipe_framebuffer_state *state)
{ {
@ -2694,7 +2715,6 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
sctx->framebuffer.compressed_cb_mask = 0; sctx->framebuffer.compressed_cb_mask = 0;
sctx->framebuffer.uncompressed_cb_mask = 0; sctx->framebuffer.uncompressed_cb_mask = 0;
sctx->framebuffer.displayable_dcc_cb_mask = 0;
sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state); sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples; sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples); sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
@ -2732,9 +2752,6 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
else else
sctx->framebuffer.uncompressed_cb_mask |= 1 << i; sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
if (tex->surface.display_dcc_offset)
sctx->framebuffer.displayable_dcc_cb_mask |= 1 << i;
/* Don't update nr_color_samples for non-AA buffers. /* Don't update nr_color_samples for non-AA buffers.
* (e.g. destination of MSAA resolve) * (e.g. destination of MSAA resolve)
*/ */
@ -3226,6 +3243,8 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0)); radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
} }
si_update_display_dcc_dirty(sctx);
sctx->framebuffer.dirty_cbufs = 0; sctx->framebuffer.dirty_cbufs = 0;
sctx->framebuffer.dirty_zsbuf = false; sctx->framebuffer.dirty_zsbuf = false;
} }

14
src/gallium/drivers/radeonsi/si_state_draw.c
View file

@ -2025,20 +2025,6 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
cik_emit_prefetch_L2(sctx, false); cik_emit_prefetch_L2(sctx, false);
} }
/* Mark the displayable dcc buffer as dirty in order to update
* it on the next call to si_flush_resource. */
if (sctx->screen->info.use_display_dcc_with_retile_blit) {
/* Don't use si_update_fb_dirtiness_after_rendering because it'll
* cause unnecessary texture decompressions on each draw. */
unsigned displayable_dcc_cb_mask = sctx->framebuffer.displayable_dcc_cb_mask;
while (displayable_dcc_cb_mask) {
unsigned i = u_bit_scan(&displayable_dcc_cb_mask);
struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
struct si_texture *tex = (struct si_texture *)surf->texture;
tex->displayable_dcc_dirty = true;
}
}
/* Clear the context roll flag after the draw call. */ /* Clear the context roll flag after the draw call. */
sctx->context_roll = false; sctx->context_roll = false;