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freedreno: PC_SO_STREAM_CNTL_STREAM_ENABLE has per-stream enable bits

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PC_SO_STREAM_CNTL.STREAM_ENABLE mirrors VPC_SO_STREAM_CNTL.STREAM_ENABLE

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17957>
This commit is contained in:
Danylo Piliaiev 2022-08-10 13:20:32 +03:00
parent 0bf2033e0d
commit 0120e7b9d9
2 changed files with 2 additions and 2 deletions
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2
src/freedreno/registers/adreno/a6xx.xml
View file

@ -2592,7 +2592,7 @@ to upconvert to 32b float internally?
<!-- New in a6xx gen3+ -->
<reg32 offset="0x9808" name="PC_SO_STREAM_CNTL">
<bitfield name="STREAM_ENABLE" pos="15" type="boolean"/>
<bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/>
</reg32>
<reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL">

2
src/gallium/drivers/freedreno/a6xx/fd6_program.c
View file

@ -281,7 +281,7 @@ setup_stream_out(struct fd_context *ctx, struct fd6_program_state *state,
* tess + xfb fails some tests if we don't emit this.
*/
OUT_RING(ring, REG_A6XX_PC_SO_STREAM_CNTL);
OUT_RING(ring, A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE);
OUT_RING(ring, A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE(0x1));
}
state->streamout_stateobj = ring;